DMA Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.099ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	1.259ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	2.004ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	115.115us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	20.890us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	1.163ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	879.591us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	145.578us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	20.890us	1	1	100.00
		dma_csr_aliasing	8.000s	879.591us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	43.000s	13.751ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	4.917m	192.479ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	7.617m	43.647ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	7.617m	43.647ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.917m	192.479ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	8.983m	212.025ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	7.617m	43.647ms	1	1	100.00
V2	dma_abort	dma_abort	6.000s	372.136us	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.383m	75.246ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	23.433us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	22.751us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	56.630us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	56.630us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	115.115us	1	1	100.00
		dma_csr_rw	2.000s	20.890us	1	1	100.00
		dma_csr_aliasing	8.000s	879.591us	1	1	100.00
		dma_same_csr_outstanding	3.000s	186.873us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	115.115us	1	1	100.00
		dma_csr_rw	2.000s	20.890us	1	1	100.00
		dma_csr_aliasing	8.000s	879.591us	1	1	100.00
		dma_same_csr_outstanding	3.000s	186.873us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	17.000s	76.819us	1	1	100.00
		dma_generic_stress	8.983m	212.025ms	1	1	100.00
		dma_handshake_stress	7.617m	43.647ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	318.869us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	92.077us	1	1	100.00
		dma_sec_cm	1.000s	138.103us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.567m	45.460ms	1	1	100.00
		dma_longer_transfer	4.000s	96.501us	1	1	100.00
		dma_stress_all_with_rand_reset	14.000s	706.844us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.70338008617751737027202600828507401633149777659806055836303890961233609246833
      Line 121, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  706843570ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  706843570ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---