EDN Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	26.403us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.810s	70.344us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.830s	13.082us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.410s	1.924ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.910s	16.747us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.990s	45.489us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.830s	13.082us	1	1	100.00
		edn_csr_aliasing	0.910s	16.747us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.660s	123.540us	1	1	100.00
V2	csrng_commands	edn_genbits	1.660s	123.540us	1	1	100.00
V2	genbits	edn_genbits	1.660s	123.540us	1	1	100.00
V2	interrupts	edn_intr	1.340s	22.651us	1	1	100.00
V2	alerts	edn_alert	1.120s	219.607us	1	1	100.00
V2	errs	edn_err	1.030s	25.596us	1	1	100.00
V2	disable	edn_disable	0.960s	107.557us	1	1	100.00
		edn_disable_auto_req_mode	1.110s	60.048us	1	1	100.00
V2	stress_all	edn_stress_all	1.790s	87.618us	1	1	100.00
V2	intr_test	edn_intr_test	0.900s	47.358us	1	1	100.00
V2	alert_test	edn_alert_test	1.060s	51.258us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.460s	81.930us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.460s	81.930us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.810s	70.344us	1	1	100.00
		edn_csr_rw	0.830s	13.082us	1	1	100.00
		edn_csr_aliasing	0.910s	16.747us	1	1	100.00
		edn_same_csr_outstanding	1.010s	38.016us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.810s	70.344us	1	1	100.00
		edn_csr_rw	0.830s	13.082us	1	1	100.00
		edn_csr_aliasing	0.910s	16.747us	1	1	100.00
		edn_same_csr_outstanding	1.010s	38.016us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.520s	241.914us	1	1	100.00
		edn_tl_intg_err	2.080s	450.577us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.020s	30.783us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.120s	219.607us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.520s	241.914us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.520s	241.914us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.520s	241.914us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.520s	241.914us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.120s	219.607us	1	1	100.00
		edn_sec_cm	3.520s	241.914us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.120s	219.607us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.080s	450.577us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	21.200s	8.751ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00