HMAC Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.820s 9.158ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.750s 103.862us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.890s 48.719us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.580s 113.682us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.180s 317.050us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.210s 35.252us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.890s 48.719us 1 1 100.00
hmac_csr_aliasing 4.180s 317.050us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.030m 1.619ms 1 1 100.00
V2 back_pressure hmac_back_pressure 12.160s 1.292ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.012m 5.535ms 1 1 100.00
hmac_test_sha384_vectors 18.400s 410.098us 1 1 100.00
hmac_test_sha512_vectors 18.900s 226.109us 1 1 100.00
hmac_test_hmac256_vectors 5.660s 807.190us 1 1 100.00
hmac_test_hmac384_vectors 10.010s 376.964us 1 1 100.00
hmac_test_hmac512_vectors 9.140s 302.837us 1 1 100.00
V2 burst_wr hmac_burst_wr 4.130s 180.740us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 10.190s 180.888us 1 1 100.00
V2 error hmac_error 28.390s 12.280ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.172m 8.105ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.820s 9.158ms 1 1 100.00
hmac_long_msg 1.030m 1.619ms 1 1 100.00
hmac_back_pressure 12.160s 1.292ms 1 1 100.00
hmac_datapath_stress 10.190s 180.888us 1 1 100.00
hmac_burst_wr 4.130s 180.740us 1 1 100.00
hmac_stress_all 17.020s 1.910ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.820s 9.158ms 1 1 100.00
hmac_long_msg 1.030m 1.619ms 1 1 100.00
hmac_back_pressure 12.160s 1.292ms 1 1 100.00
hmac_datapath_stress 10.190s 180.888us 1 1 100.00
hmac_wipe_secret 1.172m 8.105ms 1 1 100.00
hmac_test_sha256_vectors 3.012m 5.535ms 1 1 100.00
hmac_test_sha384_vectors 18.400s 410.098us 1 1 100.00
hmac_test_sha512_vectors 18.900s 226.109us 1 1 100.00
hmac_test_hmac256_vectors 5.660s 807.190us 1 1 100.00
hmac_test_hmac384_vectors 10.010s 376.964us 1 1 100.00
hmac_test_hmac512_vectors 9.140s 302.837us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.820s 9.158ms 1 1 100.00
hmac_long_msg 1.030m 1.619ms 1 1 100.00
hmac_back_pressure 12.160s 1.292ms 1 1 100.00
hmac_datapath_stress 10.190s 180.888us 1 1 100.00
hmac_burst_wr 4.130s 180.740us 1 1 100.00
hmac_error 28.390s 12.280ms 1 1 100.00
hmac_wipe_secret 1.172m 8.105ms 1 1 100.00
hmac_test_sha256_vectors 3.012m 5.535ms 1 1 100.00
hmac_test_sha384_vectors 18.400s 410.098us 1 1 100.00
hmac_test_sha512_vectors 18.900s 226.109us 1 1 100.00
hmac_test_hmac256_vectors 5.660s 807.190us 1 1 100.00
hmac_test_hmac384_vectors 10.010s 376.964us 1 1 100.00
hmac_test_hmac512_vectors 9.140s 302.837us 1 1 100.00
hmac_stress_all 17.020s 1.910ms 1 1 100.00
V2 stress_all hmac_stress_all 17.020s 1.910ms 1 1 100.00
V2 alert_test hmac_alert_test 0.580s 156.931us 1 1 100.00
V2 intr_test hmac_intr_test 0.560s 41.618us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.760s 379.188us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.760s 379.188us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.750s 103.862us 1 1 100.00
hmac_csr_rw 0.890s 48.719us 1 1 100.00
hmac_csr_aliasing 4.180s 317.050us 1 1 100.00
hmac_same_csr_outstanding 1.250s 129.903us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.750s 103.862us 1 1 100.00
hmac_csr_rw 0.890s 48.719us 1 1 100.00
hmac_csr_aliasing 4.180s 317.050us 1 1 100.00
hmac_same_csr_outstanding 1.250s 129.903us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.780s 129.073us 1 1 100.00
hmac_tl_intg_err 1.440s 427.471us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.440s 427.471us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.820s 9.158ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.080s 23.727us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.091m 23.576ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.020s 15.676us 1 1 100.00
TOTAL 28 28 100.00