I2C Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.087m	11.630ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.630s	874.883us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.940s	89.759us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.860s	31.440us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.320s	116.411us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.370s	40.108us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.060s	478.163us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.860s	31.440us	1	1	100.00
		i2c_csr_aliasing	1.370s	40.108us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.460s	75.661us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all			0	1	0.00
V2	host_maxperf	i2c_host_perf	10.126m	70.158ms	1	1	100.00
V2	host_override	i2c_host_override	0.790s	180.697us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.491m	11.645ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.695m	8.586ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.200s	204.588us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.500s	744.560us	1	1	100.00
		i2c_host_fifo_reset_rx	8.530s	262.823us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	23.950s	1.786ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.830s	1.972ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.250s	122.803us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.340s	5.529ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	2.315m	63.164ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.890s	1.711ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	26.120s	7.180ms	1	1	100.00
		i2c_target_intr_smoke	5.590s	1.061ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.340s	138.079us	1	1	100.00
		i2c_target_fifo_reset_tx	1.260s	186.874us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.211m	30.993ms	1	1	100.00
		i2c_target_stress_rd	26.120s	7.180ms	1	1	100.00
		i2c_target_intr_stress_wr	23.350s	8.064ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.800s	8.865ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.020s	3.762ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	7.160s	4.708ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	21.220s	10.128ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.990s	987.949us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.080s	297.943us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	10.126m	70.158ms	1	1	100.00
		i2c_host_perf_precise	1.430s	100.129us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.830s	1.972ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.020s	26.939us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.680s	1.059ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.000s	636.283us	1	1	100.00
		i2c_target_nack_txstretch	1.620s	168.560us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.320s	524.451us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.740s	514.310us	1	1	100.00
V2	alert_test	i2c_alert_test	0.760s	43.741us	1	1	100.00
V2	intr_test	i2c_intr_test	0.930s	46.779us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.940s	153.879us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.940s	153.879us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.940s	89.759us	1	1	100.00
		i2c_csr_rw	0.860s	31.440us	1	1	100.00
		i2c_csr_aliasing	1.370s	40.108us	1	1	100.00
		i2c_same_csr_outstanding	1.120s	126.150us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.940s	89.759us	1	1	100.00
		i2c_csr_rw	0.860s	31.440us	1	1	100.00
		i2c_csr_aliasing	1.370s	40.108us	1	1	100.00
		i2c_same_csr_outstanding	1.120s	126.150us	1	1	100.00
V2		TOTAL			31	38	81.58
V2S	tl_intg_err	i2c_tl_intg_err	1.920s	304.248us	1	1	100.00
		i2c_sec_cm	1.000s	150.736us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.920s	304.248us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.810s	1.539ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.560s	192.601us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.370s	349.868us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			40	50	80.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.36609920412411558908875136007403475646439825814688725418103607680332050289613
      Line 100, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1538963253 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1538963253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.115546669719819507401648318468958278102116251720910409406414271006501972733903
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 349868091 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 349868091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.97906310270589803388400231779362341308602325789767284896389793493983792625487
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  75661063 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  75661063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.21372718726285485953161661181693329727607085684922356471997432025463187635080
      Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.97981109960589456297941367795317927213576327877332387643161531793151766227522
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 5529255861 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 5529255861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.100917872452894706976691153712990165346663163450865076851971356378278618169923
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 192601200 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 163 [0xa3])
        UVM_INFO @ 192601200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.70578487648258316964309822600054917308974330063722135919963414784627203929326
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10127590115 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10127590115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[NOA] Null object access has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.103210517379602592621821095652018332473911229946006194734152478171874179739564
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        Error-[NOA] Null object access
        src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
          The object at dereference depth 0 is being used before it was
          constructed/allocated.
          Please make sure that the object is allocated before using it.
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_tx_stretch_ctrl has 1 failures.

    • 0.i2c_target_tx_stretch_ctrl.112350058164034569083316483544190346390838645985077971922140234677556265140124
      Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.61053925158615430635628181641239712650132244709204552051963738562189287917611
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 168559930 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 168559930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---