KEYMGR Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 13.230s 1.147ms 1 1 100.00
V1 random keymgr_random 2.380s 64.280us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.830s 26.978us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.040s 26.793us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 10.370s 1.397ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 5.310s 516.206us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.090s 44.061us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.040s 26.793us 1 1 100.00
keymgr_csr_aliasing 5.310s 516.206us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 5.650s 172.505us 1 1 100.00
V2 sideload keymgr_sideload 2.090s 41.395us 1 1 100.00
keymgr_sideload_kmac 1.990s 177.173us 1 1 100.00
keymgr_sideload_aes 3.480s 138.811us 1 1 100.00
keymgr_sideload_otbn 2.060s 49.319us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 2.150s 747.626us 1 1 100.00
V2 lc_disable keymgr_lc_disable 3.910s 253.055us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.800s 393.529us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.870s 84.689us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 4.670s 242.831us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 2.460s 96.019us 1 1 100.00
V2 stress_all keymgr_stress_all 16.710s 1.867ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.760s 19.988us 1 1 100.00
V2 alert_test keymgr_alert_test 0.770s 25.221us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.460s 515.721us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.460s 515.721us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.830s 26.978us 1 1 100.00
keymgr_csr_rw 1.040s 26.793us 1 1 100.00
keymgr_csr_aliasing 5.310s 516.206us 1 1 100.00
keymgr_same_csr_outstanding 1.340s 40.445us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.830s 26.978us 1 1 100.00
keymgr_csr_rw 1.040s 26.793us 1 1 100.00
keymgr_csr_aliasing 5.310s 516.206us 1 1 100.00
keymgr_same_csr_outstanding 1.340s 40.445us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 5.900s 846.459us 1 1 100.00
keymgr_tl_intg_err 3.070s 954.096us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.480s 186.985us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.480s 186.985us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.480s 186.985us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.480s 186.985us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 4.020s 237.780us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.070s 954.096us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.480s 186.985us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 5.650s 172.505us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 2.380s 64.280us 1 1 100.00
keymgr_csr_rw 1.040s 26.793us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 2.380s 64.280us 1 1 100.00
keymgr_csr_rw 1.040s 26.793us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 2.380s 64.280us 1 1 100.00
keymgr_csr_rw 1.040s 26.793us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 3.910s 253.055us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 4.670s 242.831us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 4.670s 242.831us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 2.380s 64.280us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.690s 108.370us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 3.560s 257.552us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 3.910s 253.055us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 3.560s 257.552us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 3.560s 257.552us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 3.560s 257.552us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 5.900s 846.459us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 3.560s 257.552us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 9.350s 1.472ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00