| V1 |
smoke |
keymgr_dpe_smoke |
22.250s |
1.934ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.920s |
119.249us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.940s |
35.775us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
11.970s |
597.044us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.020s |
81.661us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.660s |
132.556us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.940s |
35.775us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.020s |
81.661us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.920s |
38.202us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.810s |
48.567us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.260s |
44.602us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.260s |
44.602us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.920s |
119.249us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
35.775us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.020s |
81.661us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.770s |
97.776us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.920s |
119.249us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
35.775us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.020s |
81.661us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.770s |
97.776us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
12.340s |
2.256ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
2.060s |
536.080us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.180s |
41.559us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.180s |
41.559us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.180s |
41.559us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.180s |
41.559us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
6.450s |
1.025ms |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
12.340s |
2.256ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
12.340s |
2.256ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |