KMAC/MASKED Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	18.130s	689.874us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.880s	78.047us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.880s	72.808us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.060s	490.973us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.480s	226.690us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.100s	103.326us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.880s	72.808us	1	1	100.00
		kmac_csr_aliasing	3.480s	226.690us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.910s	18.600us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.330s	45.710us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	27.567m	19.601ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.105m	14.630ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.992m	267.332ms	1	1	100.00
		kmac_test_vectors_sha3_256	35.880s	7.743ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.132m	34.421ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.150s	4.793ms	1	1	100.00
		kmac_test_vectors_shake_128	37.503m	95.348ms	1	1	100.00
		kmac_test_vectors_shake_256	5.196m	40.907ms	1	1	100.00
		kmac_test_vectors_kmac	2.360s	83.232us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.350s	109.769us	1	1	100.00
V2	sideload	kmac_sideload	3.612m	47.496ms	1	1	100.00
V2	app	kmac_app	42.440s	2.027ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.283m	8.167ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.049m	6.666ms	1	1	100.00
V2	error	kmac_error	2.260m	5.037ms	1	1	100.00
V2	key_error	kmac_key_error	1.150s	62.344us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.710s	122.903us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.030s	25.524us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.500s	45.712us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.070s	14.805ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.570s	126.359us	1	1	100.00
V2	stress_all	kmac_stress_all	9.943m	10.000ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.890s	17.088us	1	1	100.00
V2	alert_test	kmac_alert_test	0.890s	16.493us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.660s	57.240us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.660s	57.240us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.880s	78.047us	1	1	100.00
		kmac_csr_rw	0.880s	72.808us	1	1	100.00
		kmac_csr_aliasing	3.480s	226.690us	1	1	100.00
		kmac_same_csr_outstanding	1.640s	426.229us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.880s	78.047us	1	1	100.00
		kmac_csr_rw	0.880s	72.808us	1	1	100.00
		kmac_csr_aliasing	3.480s	226.690us	1	1	100.00
		kmac_same_csr_outstanding	1.640s	426.229us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.150s	36.045us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.150s	36.045us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.150s	36.045us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.150s	36.045us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.330s	1.137ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	30.390s	6.562ms	1	1	100.00
		kmac_tl_intg_err	2.060s	134.244us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.060s	134.244us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.570s	126.359us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	18.130s	689.874us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.612m	47.496ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.150s	36.045us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	30.390s	6.562ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	30.390s	6.562ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	30.390s	6.562ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	18.130s	689.874us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.570s	126.359us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	30.390s	6.562ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.109m	72.235ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	18.130s	689.874us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.737m	19.682ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.2090745329531719098583694302039732948041004742249986700393092564985170725398
      Line 204, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19681545922 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 19681545922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---