KMAC/UNMASKED Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	26.030s	8.309ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.990s	21.208us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.970s	27.207us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.270s	1.177ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.580s	982.856us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.080s	347.336us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.970s	27.207us	1	1	100.00
		kmac_csr_aliasing	6.580s	982.856us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.670s	36.361us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.030s	21.372us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.795m	177.225ms	1	1	100.00
V2	burst_write	kmac_burst_write	15.400s	2.239ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.730m	374.317ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.210s	4.354ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.690s	876.868us	1	1	100.00
		kmac_test_vectors_sha3_512	13.981m	108.447ms	1	1	100.00
		kmac_test_vectors_shake_128	33.212m	471.601ms	1	1	100.00
		kmac_test_vectors_shake_256	1.190m	1.659ms	1	1	100.00
		kmac_test_vectors_kmac	2.020s	407.115us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.760s	223.275us	1	1	100.00
V2	sideload	kmac_sideload	55.590s	8.049ms	1	1	100.00
V2	app	kmac_app	1.684m	6.734ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.134m	97.703ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.859m	7.472ms	1	1	100.00
V2	error	kmac_error	23.730s	4.900ms	1	1	100.00
V2	key_error	kmac_key_error	8.260s	13.614ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.412m	10.027ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.630s	397.054us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	5.390s	415.159us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.340s	204.964us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.090s	83.595us	1	1	100.00
V2	stress_all	kmac_stress_all	15.360s	12.280ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.790s	46.295us	1	1	100.00
V2	alert_test	kmac_alert_test	0.840s	75.103us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.660s	37.212us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.660s	37.212us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.990s	21.208us	1	1	100.00
		kmac_csr_rw	0.970s	27.207us	1	1	100.00
		kmac_csr_aliasing	6.580s	982.856us	1	1	100.00
		kmac_same_csr_outstanding	2.000s	120.067us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.990s	21.208us	1	1	100.00
		kmac_csr_rw	0.970s	27.207us	1	1	100.00
		kmac_csr_aliasing	6.580s	982.856us	1	1	100.00
		kmac_same_csr_outstanding	2.000s	120.067us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.600s	530.529us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.600s	530.529us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.600s	530.529us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.600s	530.529us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	105.819us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	42.050s	43.081ms	1	1	100.00
		kmac_tl_intg_err	2.000s	251.699us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.000s	251.699us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.090s	83.595us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	26.030s	8.309ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	55.590s	8.049ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.600s	530.529us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.050s	43.081ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.050s	43.081ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.050s	43.081ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	26.030s	8.309ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.090s	83.595us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.050s	43.081ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.121m	10.338ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	26.030s	8.309ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.072m	19.588ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.66972416474997135021161495760983795344608765274470468777615876608603312818996
      Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10027125463 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5ea5000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10027125463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---