MBX Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.333m	6.878ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	1.000s	20.759us	1	1	100.00
V1	csr_rw	mbx_csr_rw	1.000s	14.076us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	2.000s	220.172us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	22.455us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	32.978us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	1.000s	14.076us	1	1	100.00
		mbx_csr_aliasing	2.000s	22.455us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	9.000s	163.411us	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	1.300m	9.114ms	1	1	100.00
V2	mbx_imbx_oob	mbx_imbx_oob	44.000s	30.077ms	0	1	0.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	10.000s	3.375ms	1	1	100.00
V2	alert_test	mbx_alert_test	1.000s	17.962us	1	1	100.00
V2	intr_test	mbx_intr_test	1.000s	37.501us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.000s	770.580us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.000s	770.580us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	1.000s	20.759us	1	1	100.00
		mbx_csr_rw	1.000s	14.076us	1	1	100.00
		mbx_csr_aliasing	2.000s	22.455us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	17.853us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	1.000s	20.759us	1	1	100.00
		mbx_csr_rw	1.000s	14.076us	1	1	100.00
		mbx_csr_aliasing	2.000s	22.455us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	17.853us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	502.093us	1	1	100.00
		mbx_sec_cm	2.000s	37.489us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			14	16	87.50

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.63629788777823570089356491779903887107241711748334442361442767181568565460987
      Line 154, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 163411455 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
        UVM_ERROR @ 163411455 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
        UVM_INFO @ 163411455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.90465410464695271676412294272081513776660825671961740682014431126814468928077
      Line 230, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 30076794362 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 30076794362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---