ROM_CTRL/32KB Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.430s	177.805us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	4.550s	564.950us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.380s	208.869us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.970s	131.719us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.060s	168.476us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.020s	322.408us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.380s	208.869us	1	1	100.00
		rom_ctrl_csr_aliasing	5.060s	168.476us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.970s	196.027us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.660s	180.683us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.710s	1.042ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	14.700s	6.089ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.910s	1.046ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.730s	127.128us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.440s	2.099ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.440s	2.099ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	4.550s	564.950us	1	1	100.00
		rom_ctrl_csr_rw	3.380s	208.869us	1	1	100.00
		rom_ctrl_csr_aliasing	5.060s	168.476us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.140s	168.201us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	4.550s	564.950us	1	1	100.00
		rom_ctrl_csr_rw	3.380s	208.869us	1	1	100.00
		rom_ctrl_csr_aliasing	5.060s	168.476us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.140s	168.201us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.240s	1.660ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.816m	647.921us	0	1	0.00
		rom_ctrl_tl_intg_err	23.270s	788.312us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.816m	647.921us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.816m	647.921us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.816m	647.921us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.816m	647.921us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.430s	177.805us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.430s	177.805us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.430s	177.805us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	23.270s	788.312us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
		rom_ctrl_kmac_err_chk	9.910s	1.046ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	36.810s	881.524us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.240s	1.660ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.816m	647.921us	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.718m	4.917ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.49990185294151886710532132296814194844207180697862610395133519364117170923958
      Line 91, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 881524323 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 881524323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.74272113703495630525933406199882331718197963263423188040849030519014930416709
      Line 222, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 11831184ps failed at 11831184ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11831184ps failed at 11831184ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'