2c4c18b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.940s | 471.490us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.830s | 33.734us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.700s | 61.233us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.010s | 3.394ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.730s | 15.045us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.240s | 34.531us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.700s | 61.233us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.730s | 15.045us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.820s | 62.903us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.490s | 1.460ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 3.721m | 210.794ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 3.721m | 210.794ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 3.350s | 10.304ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.760s | 40.894us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.590s | 134.172us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.420s | 36.000us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.420s | 36.000us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.830s | 33.734us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.700s | 61.233us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 15.045us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.720s | 35.919us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.830s | 33.734us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.700s | 61.233us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 15.045us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.720s | 35.919us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.790s | 38.245us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.420s | 388.830us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 388.830us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.820s | 625.185us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.860s | 735.306us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 15.590s | 3.507ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 15 | 19 | 78.95 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.107830516730403286327819239714161802896259003689656062739216316556208437005565
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 625184835 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5519f504) == 0x1
UVM_INFO @ 625184835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.16196321028651706010300708299448585180037325433339098448517126042666720661570
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 62902507 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8b68f504) == 0x1
UVM_INFO @ 62902507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.76980232241182145105207831969733307884902080094375702117208761547125360838013
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 735306369 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 735306369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:
0.rv_timer_stress_all_with_rand_reset.104422200009851505690447986447010234303669662292685710890506740681188499826037
Line 168, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3506924784 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 3506924784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---