SPI_DEVICE/1R1W Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.699m	46.600ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.080s	44.123us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.210s	210.364us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.120s	1.467ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.630s	2.131ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.840s	465.303us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.210s	210.364us	1	1	100.00
		spi_device_csr_aliasing	15.630s	2.131ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.860s	33.782us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.880s	273.581us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.840s	117.752us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.730s	1.191us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.660s	5.619us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.680s	313.700us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.680s	313.700us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	14.890s	8.804ms	1	1	100.00
		spi_device_tpm_sts_read	0.750s	81.303us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.550s	1.755ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	14.010s	24.821ms	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.710s	32.339us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.710s	32.339us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.900s	555.190us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.900s	555.190us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.900s	555.190us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.900s	555.190us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.900s	555.190us	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.490s	677.168us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	17.780s	16.909ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	17.780s	16.909ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	17.780s	16.909ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.970s	146.953us	1	1	100.00
		spi_device_read_buffer_direct	13.420s	1.890ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	17.780s	16.909ms	1	1	100.00
		spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	quad_spi	spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	dual_spi	spi_device_flash_all	7.130s	791.432us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.320s	1.997ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.320s	1.997ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.699m	46.600ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	21.210s	2.902ms	1	1	100.00
V2	stress_all	spi_device_stress_all	51.870s	90.450ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.700s	48.872us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.900s	60.667us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.790s	113.025us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.790s	113.025us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.080s	44.123us	1	1	100.00
		spi_device_csr_rw	1.210s	210.364us	1	1	100.00
		spi_device_csr_aliasing	15.630s	2.131ms	1	1	100.00
		spi_device_same_csr_outstanding	2.290s	52.369us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.080s	44.123us	1	1	100.00
		spi_device_csr_rw	1.210s	210.364us	1	1	100.00
		spi_device_csr_aliasing	15.630s	2.131ms	1	1	100.00
		spi_device_same_csr_outstanding	2.290s	52.369us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.580s	117.323us	1	1	100.00
		spi_device_tl_intg_err	14.330s	981.599us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.330s	981.599us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	25.510s	2.272ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.39743685667398609719166981129067341340662080434212945766135787795552121106310
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    953890 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[44])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    953890 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    953890 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[940])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.3118441175990823276693817509008898278346376030013897464104635870229008412544
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3032912 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x433c1d [10000110011110000011101] vs 0x0 [0])
        UVM_ERROR @   3053912 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x749bac [11101001001101110101100] vs 0x0 [0])
        UVM_ERROR @   3079912 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x314235 [1100010100001000110101] vs 0x0 [0])
        UVM_ERROR @   3093912 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x29e2e2 [1010011110001011100010] vs 0x0 [0])
        UVM_ERROR @   3184912 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf8eb0b [111110001110101100001011] vs 0x0 [0])