SPI_HOST Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	20.000s	1.932ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	18.702us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	24.392us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	166.461us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	46.694us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	30.153us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	24.392us	1	1	100.00
		spi_host_csr_aliasing	1.000s	46.694us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	16.159us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	18.679us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	65.603us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	147.787us	1	1	100.00
		spi_host_error_cmd	1.000s	22.227us	1	1	100.00
		spi_host_event	12.000s	424.429us	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	72.539us	1	1	100.00
V2	speed	spi_host_speed	2.000s	72.539us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	72.539us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	391.300us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	26.360us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	72.539us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	72.539us	1	1	100.00
V2	duplex	spi_host_smoke	20.000s	1.932ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	20.000s	1.932ms	1	1	100.00
V2	stress_all	spi_host_stress_all	45.000s	1.313ms	1	1	100.00
V2	spien	spi_host_spien	3.000s	238.542us	1	1	100.00
V2	stall	spi_host_status_stall	1.250m	10.429ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	103.731us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	147.787us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	15.787us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	29.199us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	271.716us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	271.716us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	18.702us	1	1	100.00
		spi_host_csr_rw	2.000s	24.392us	1	1	100.00
		spi_host_csr_aliasing	1.000s	46.694us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	188.069us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	18.702us	1	1	100.00
		spi_host_csr_rw	2.000s	24.392us	1	1	100.00
		spi_host_csr_aliasing	1.000s	46.694us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	188.069us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	694.114us	1	1	100.00
		spi_host_sec_cm	1.000s	122.203us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	694.114us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.667m	7.278ms	1	1	100.00
		TOTAL			26	26	100.00