SRAM_CTRL/MAIN Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.880s	4.384ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.630s	17.024us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.960s	13.183us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.400s	102.518us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.900s	14.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.370s	371.069us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.960s	13.183us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	14.371us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.221m	4.110ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	57.980s	5.141ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	18.810s	1.945ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.346m	45.391ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.883m	169.603ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.241m	47.775ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	32.440s	9.987ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.103m	33.758ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	19.790s	3.392ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.787m	239.455ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.014m	843.508us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	31.120s	1.517ms	1	1	100.00
		sram_ctrl_throughput_w_readback	36.520s	874.130us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.060m	31.314ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.430s	3.042ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	37.246m	128.327ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.950s	14.832us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.900s	153.559us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.900s	153.559us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.630s	17.024us	1	1	100.00
		sram_ctrl_csr_rw	0.960s	13.183us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	14.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.970s	37.833us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.630s	17.024us	1	1	100.00
		sram_ctrl_csr_rw	0.960s	13.183us	1	1	100.00
		sram_ctrl_csr_aliasing	0.900s	14.371us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.970s	37.833us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.540s	19.419ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.700s	9.683us	0	1	0.00
		sram_ctrl_tl_intg_err	1.750s	388.629us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.700s	9.683us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.750s	388.629us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.060m	31.314ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.060m	31.314ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.960s	13.183us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.103m	33.758ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.103m	33.758ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.103m	33.758ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	32.440s	9.987ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.700s	1.331ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.540s	19.419ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.160s	1.404ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.880s	4.384ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.880s	4.384ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.103m	33.758ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.700s	9.683us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	32.440s	9.987ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.700s	9.683us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.700s	9.683us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.880s	4.384ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.700s	9.683us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.290s	1.141ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.51973425336819023180850752016049758012246015255120634473571681875930567650214
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   9682586 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   9682586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---