SRAM_CTRL/RET Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.040s	845.314us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.870s	47.006us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.750s	17.639us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.470s	43.837us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	26.456us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.180s	157.334us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.750s	17.639us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	26.456us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.330s	228.256us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.520s	227.397us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.378m	47.157ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.656m	2.311ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	45.990s	1.855ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.850m	9.145ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.300s	597.972us	1	1	100.00
V2	executable	sram_ctrl_executable	5.918m	10.320ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.810s	320.201us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.092m	6.281ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.540s	59.390us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	59.930s	1.456ms	1	1	100.00
		sram_ctrl_throughput_w_readback	56.210s	292.199us	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.104m	33.404ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.000s	79.223us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	44.397m	31.625ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.770s	85.515us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.740s	1.912ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.740s	1.912ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.870s	47.006us	1	1	100.00
		sram_ctrl_csr_rw	0.750s	17.639us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	26.456us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.910s	21.329us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.870s	47.006us	1	1	100.00
		sram_ctrl_csr_rw	0.750s	17.639us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	26.456us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.910s	21.329us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.470s	823.033us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.610s	1.291us	0	1	0.00
		sram_ctrl_tl_intg_err	1.840s	372.358us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.610s	1.291us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.840s	372.358us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.104m	33.404ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.104m	33.404ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.750s	17.639us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.918m	10.320ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.918m	10.320ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.918m	10.320ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.300s	597.972us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.000s	134.925us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.470s	823.033us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.090s	33.813us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.040s	845.314us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.040s	845.314us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.918m	10.320ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.610s	1.291us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.300s	597.972us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.610s	1.291us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.610s	1.291us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.040s	845.314us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.610s	1.291us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.336m	23.674ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.70031586570542195808789654553506882663511599363880608637504242350747283677897
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1291003 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1291003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---