UART Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: 2c4c18b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	10.740s	5.363ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.680s	14.239us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.640s	41.360us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.300s	849.640us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.720s	63.642us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.010s	112.773us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	41.360us	1	1	100.00
		uart_csr_aliasing	0.720s	63.642us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	31.400s	21.167ms	1	1	100.00
V2	parity	uart_smoke	10.740s	5.363ms	1	1	100.00
		uart_tx_rx	31.400s	21.167ms	1	1	100.00
V2	parity_error	uart_intr	7.030s	18.855ms	1	1	100.00
		uart_rx_parity_err	1.240m	57.220ms	1	1	100.00
V2	watermark	uart_tx_rx	31.400s	21.167ms	1	1	100.00
		uart_intr	7.030s	18.855ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.514m	126.543ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	35.880s	37.436ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	31.930s	52.379ms	1	1	100.00
V2	rx_frame_err	uart_intr	7.030s	18.855ms	1	1	100.00
V2	rx_break_err	uart_intr	7.030s	18.855ms	1	1	100.00
V2	rx_timeout	uart_intr	7.030s	18.855ms	1	1	100.00
V2	perf	uart_perf	2.209m	6.761ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.040s	3.746ms	1	1	100.00
V2	line_loopback	uart_loopback	3.040s	3.746ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	21.610s	116.924ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.580s	2.940ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.630s	2.370ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	39.650s	6.869ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.193m	99.474ms	1	1	100.00
V2	stress_all	uart_stress_all	49.510s	51.927ms	1	1	100.00
V2	alert_test	uart_alert_test	0.880s	14.768us	1	1	100.00
V2	intr_test	uart_intr_test	0.790s	12.465us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.710s	316.112us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.710s	316.112us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.680s	14.239us	1	1	100.00
		uart_csr_rw	0.640s	41.360us	1	1	100.00
		uart_csr_aliasing	0.720s	63.642us	1	1	100.00
		uart_same_csr_outstanding	0.920s	61.761us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.680s	14.239us	1	1	100.00
		uart_csr_rw	0.640s	41.360us	1	1	100.00
		uart_csr_aliasing	0.720s	63.642us	1	1	100.00
		uart_same_csr_outstanding	0.920s	61.761us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.100s	189.364us	1	1	100.00
		uart_tl_intg_err	1.030s	95.580us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.030s	95.580us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	50.080s	3.491ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.75069406815496281694531530417401075446780798212592583297166147820053984424436
      Line 111, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 922919116 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 922929116 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 922939116 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 938709116 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 938709116 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1