CHIP Simulation Results

Monday November 03 2025 16:06:17 UTC

GitHub Revision: `2c4c18b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.350m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.350m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.122m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	35.814s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	36.924s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.045m	4.722ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.045m	4.722ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.045m	4.722ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.870s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	13.077s		0	1	0.00
		chip_sw_example_concurrency	6.115m	4.798ms	1	1	100.00
		chip_sw_uart_smoketest_signed	9.346s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.090s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.460s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.460s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.720s	57.645us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.779m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.943m	7.622ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.609m	5.647ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.890s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.368s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	33.195s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.829s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	2.820s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.820s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.302m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.059m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.109m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.109m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.507m	3.232ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.457m	4.924ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.567m	10.264ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.248s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.893s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.666m	8.024ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.165m	4.716ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	33.739m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	33.739m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.976s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.903m	4.949ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.903m	4.949ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.868m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.559m	3.691ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.250m	3.882ms	1	1	100.00
		chip_sw_aes_idle	4.723m	5.199ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.486m	4.250ms	1	1	100.00
		chip_sw_kmac_idle	6.586m	5.550ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	16.416m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	17.175m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	15.810m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	18.411m	11.639ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.764s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.812s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.251s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.430s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.329s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.678s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.343s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.764s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.812s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.251s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.430s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.329s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.678s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.343s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	37.050s	10.280us	0	1	0.00
		chip_sw_aes_enc_jitter_en	39.390s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.930s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.900s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.710s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.865s		0	1	0.00
		chip_sw_clkmgr_jitter	5.170m	4.633ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.972m	5.152ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	42.100s	10.320us	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	40.960s	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	38.950s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	38.990s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.110s	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.720s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	10.478s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.775s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.673s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.374s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	12.058m	4.748ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	13.904m	11.701ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.903m	4.949ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.027s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	13.904m	11.701ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.921s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	8.913s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.079s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.198s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.032s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	12.058m	4.748ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.567m	10.264ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.789m	5.319ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.987m	5.099ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	5.291m	4.370ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.531m	3.182ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	12.058m	4.748ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	9.432s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.776s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	12.058m	4.748ms	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	9.565s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	5.291m	4.370ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.439s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.417s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.129s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	9.262s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	9.593s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9.486s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.776s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	21.964s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.957m	5.497ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.290s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.472s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.233s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.102s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.928m	4.561ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	12.483m	10.915ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.906s		0	1	0.00
		chip_prim_tl_access	18.312m	19.149ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.764s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.812s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.251s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.430s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.329s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.678s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.343s		0	1	0.00
		chip_rv_dm_lc_disabled	6.666m	8.024ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.339m	4.122ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	39.390s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.558m	5.136ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.723m	5.199ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.229m	3.367ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	37.930s	10.260us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.486m	4.250ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.401m	5.093ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.795m	4.143ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	44.710s	10.120us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.928m	4.561ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.120s	10.160us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.064m	5.434ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	6.586m	5.550ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.841m	5.042ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.841m	5.042ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	16.329s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.220m	5.276ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.800s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.928m	4.561ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.900s	10.300us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.519m	18.236ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	37.050s	10.280us	0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.250m	3.882ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.250m	3.882ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.250m	3.882ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.122m	5.233ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.483m	10.915ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.483m	10.915ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.816m	5.447ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.865s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.906s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	12.058m	4.748ms	0	1	0.00
		chip_sw_data_integrity_escalation	2.109m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.122m	5.233ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.928m	4.561ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.816m	5.447ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.745m	4.321ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.122m	5.233ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.928m	4.561ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.816m	5.447ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.745m	4.321ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.968s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	21.964s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.290s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.472s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.233s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.102s		0	1	0.00
		chip_sw_lc_ctrl_transition	21.347s		0	1	0.00
		chip_prim_tl_access	18.312m	19.149ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	18.312m	19.149ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	10.736s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	10.766s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.775s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	37.050s	10.280us	0	1	0.00
		chip_sw_aes_enc_jitter_en	39.390s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.930s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	37.900s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.710s	10.120us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.865s		0	1	0.00
		chip_sw_clkmgr_jitter	5.170m	4.633ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	5.338m	3.981ms	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	5.338m	3.981ms	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.787m	4.433ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.704m	3.935ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.057m	4.617ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.087m	4.404ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.798m	4.690ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.900m	5.262ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.745m	4.321ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.789m	5.319ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.789m	5.319ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.356m	3.835ms	1	1	100.00
		chip_sw_aon_timer_smoketest	5.208m	3.678ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.635m	3.358ms	1	1	100.00
		chip_sw_csrng_smoketest	3.818m	3.207ms	1	1	100.00
		chip_sw_gpio_smoketest	5.689m	5.706ms	1	1	100.00
		chip_sw_hmac_smoketest	5.505m	3.790ms	1	1	100.00
		chip_sw_kmac_smoketest	4.681m	4.513ms	1	1	100.00
		chip_sw_otbn_smoketest	5.477m	5.305ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.223m	4.881ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.472m	4.225ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.530m	5.387ms	1	1	100.00
		chip_sw_rstmgr_smoketest	4.886m	4.693ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.656m	4.090ms	1	1	100.00
		chip_sw_uart_smoketest	3.908m	4.871ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.372s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	9.346s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.779m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.272s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.949m	4.332ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.646m	5.007ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.473m	3.748ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.582m	5.468ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.473s		0	1	0.00
		chip_rv_dm_lc_disabled	6.666m	8.024ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	10.816s		0	1	0.00
		chip_sw_lc_walkthrough_prod	10.305s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.611s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.089s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.473s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	10.795m	8.580ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	8.491m	7.286ms	1	1	100.00
		rom_volatile_raw_unlock	9.679s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	9.493s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.809m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.701m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	4.515m	3.962ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	4.515m	3.962ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.460s		0	1	0.00
		chip_same_csr_outstanding	10.250s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.460s		0	1	0.00
		chip_same_csr_outstanding	10.250s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.779m	263.025us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.520s	11.665us	1	1	100.00
		xbar_smoke_large_delays	4.366m	2.303ms	1	1	100.00
		xbar_smoke_slow_rsp	6.152m	2.227ms	1	1	100.00
		xbar_random_zero_delays	1.226m	59.299us	1	1	100.00
		xbar_random_large_delays	19.390m	9.718ms	1	1	100.00
		xbar_random_slow_rsp	11.636m	4.042ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.572m	167.584us	1	1	100.00
		xbar_error_and_unmapped_addr	57.170s	41.191us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.068m	162.053us	1	1	100.00
		xbar_error_and_unmapped_addr	57.170s	41.191us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.423m	728.369us	1	1	100.00
		xbar_access_same_device_slow_rsp	44.040m	16.910ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.268m	68.194us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.774m	268.489us	1	1	100.00
		xbar_stress_all_with_error	26.380m	4.234ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	9.135m	203.937us	1	1	100.00
		xbar_stress_all_with_reset_error	20.646m	1.724ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.564s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.252s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.477s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.914s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	9.398s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.813s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.424s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.245s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.974s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.159s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	9.308s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.990s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.876s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	45.017s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	55.747s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	56.051s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	49.817s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.052m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	50.529s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	54.982s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	46.518s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	56.052s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	45.760s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	39.392s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	31.915s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	29.177s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	24.956s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	24.993s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.049s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.565s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.212s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	10.483s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.813s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.289s		0	1	0.00
		rom_e2e_asm_init_dev	12.413s		0	1	0.00
		rom_e2e_asm_init_prod	10.964s		0	1	0.00
		rom_e2e_asm_init_prod_end	9.863s		0	1	0.00
		rom_e2e_asm_init_rma	10.051s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	9.485s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.050s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	9.588s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.821s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	7.013m	5.773ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.653m	4.758ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.279s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.317s		0	1	0.00
		rom_e2e_jtag_debug_rma	9.817s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.880s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	12.058m	4.748ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	9.928s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.051m	5.730ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	11.324s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.270s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.279s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.317s		0	1	0.00
		rom_e2e_jtag_debug_rma	9.817s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	9.613s		0	1	0.00
		rom_e2e_jtag_inject_dev	9.649s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.030s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.133s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	11.216m	5.505ms	0	1	0.00
		chip_sw_entropy_src_kat_test	6.387m	5.255ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	5.239m	4.523ms	1	1	100.00
		chip_plic_all_irqs_0	12.381m	7.388ms	1	1	100.00
		chip_plic_all_irqs_10	12.825m	6.247ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.566m	4.029ms	1	1	100.00
		chip_sw_dma_abort	4.764m	5.303ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	9.635s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	9.737s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.612s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.052s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.501s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.396s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	9.761s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.414s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.651s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.509s		0	1	0.00
		chip_sw_entropy_src_smoketest	6.437m	5.906ms	1	1	100.00
		chip_sw_mbx_smoketest	6.656m	5.604ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 130 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.56573933241339785080407917104256618934896975015430196661115710178889795191567
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  [1 / 1] no actions running
  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 3.081s, Critical Path: 0.14s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.46537938841232715955262845373839709721666359804585201788966859307783778427274
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 116.712s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.15504988168618851561969213643029865615908714021110150430321180419466381918998
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 128.722s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.79204942340645836834911413518460725156619080285653912552185207250762703067351
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 113.219s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.14119938848267012188542005628926655259575768678948147594112406266368472291277
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 132.144s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 125 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:
- Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.
  - 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.42577374872697243004682141894858590461801937435551413543472320541286705107906
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.61808185960037987818545622391787165570570154093473791885801382461724357475560
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.70424713146616954716249916611221842910312570154015733051264891402582285206108
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.27455647791872578110333657459310038243656665334393167989785975705539976037901
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.113192790252218781619464042106757547115577737209540078696826052569895686628615
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '(reset_cause == HwReq)' has 6 failures:
- Test chip_sw_rstmgr_sw_req has 1 failures.
  - 0.chip_sw_rstmgr_sw_req.87956653334654666830825717533362345204225381176064465587052002578616091416975
    Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 5098.755672 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 5098.755672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.101518908504179089947866627683146037324294353396597056736628580166218803700419
    Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 4369.773072 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 4369.773072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.37965032214211757399627343786243748855955941807267039257158456335227612924720
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 5318.937048 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 5318.937048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.86237863842914598864828690057181545300675264704110890488678204214205987243830
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 4561.232112 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 4561.232112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.79263524110327718549094572890908108019504441693048222446667469733560090399084
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
      Offending '(reset_cause == HwReq)'
  UVM_ERROR @ 5497.217880 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
  UVM_INFO @ 5497.217880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.47049826827856189077924161213927900558367062236110715459792784277153565957512
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.85096880528512171532816913844645100157534316219581862298467201381370103673592
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.105082696732707861033372483435137014249093893507737859855747875793969787538729
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.103410777718334854599042664680709418433107637445724611719284333870529496408792
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.562053 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.562053 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.64915978580887498500691838598622534716457708970733551445827215188723361812678
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.876064 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.876064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.40194640730894399474458977848533866119104802200456796515406000204534625305337
Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.752811 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.752811 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]' has 2 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.5498038976539444698549152013334902128028074989331850076138521074309215090779
    Line 444, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
      Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 4747.672176 us: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
  UVM_INFO @ 4747.672176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.36637612456673119847083751534599690933934648238656847019548729866072031776868
    Line 442, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
      Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 5504.775558 us: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
  UVM_INFO @ 5504.775558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:436) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.54221011836345499021784701049012094412620130122432942781517362330230942747990
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 18018.534944 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.534944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.
  - 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.24370426141276385196340059168758113613796580547916776088349714645197020834915
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log
```
  UVM_ERROR @ 18018.401882 us: (chip_sw_base_vseq.sv:436) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.401882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.79951588474396252039505763800190272456272764279374180141723595386834439227762
Line 6256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3231.700550 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: 'h30480000  a_data: 'h914a751b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h0  a_user: 'h26924  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3231.700550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.45814028749294568967374027520715117946270992550263347691274752377468744554994
Line 6256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4923.513586 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: 'h30480000  a_data: 'hbe7dadc2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h1  a_user: 'h248eb  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4923.513586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.29376189438949374044465912607511768108314683017254055733651655522379435342196
    Line 567, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.41953968985007165778278174259714875647770258938073572203064352962919946595001
    Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5647.314254 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5647.314254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.92413310621633767538414262978599071498391298933414880400397429622061562892823
    Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 5730.492012 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 5730.492012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.21120570998888017514660985731550302515091682779700460925203554258823118293189
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 3981.189000 us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
  UVM_INFO @ 3981.189000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.490591033034187729359447071978364548618763234980583930173820901767405641841
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4433.070802 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4433.070802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.24570264430609836326984473311531916359184842788064737337027315696098009039105
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3934.743105 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3934.743105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.92462130463390193350817695773220321377363761881537601726737008009967134345963
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4949.113248 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4949.113248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.113329554434357390800901104208817882033273550062265879184198524376402108760813
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4403.558064 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4403.558064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.82901435236153540318089477577263359500607427880378583645551970496446662091507
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.103163968295906946504380832775006782321703242417896315544703405200520524362660
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3962.286409 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3962.286409 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.80353863949559352742591803831826320513684366583071126753891946780020818075862
    Line 233, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 8024.043555 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40634 read out mismatch
  UVM_INFO @ 8024.043555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.54124557186404943614383176566708567576837208336939563437144490387940708918400
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.89265522856119548259454889931594339550813831137611315177025249800790472753621
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_ERROR @ 5303.478164 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 5303.478164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```