DMA Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	1.199ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	1.810ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	561.074us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	19.293us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	21.071us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	597.101us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	157.792us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	144.471us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	21.071us	1	1	100.00
		dma_csr_aliasing	6.000s	157.792us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	47.000s	29.767ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	3.550m	20.304ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	5.367m	347.466ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.367m	347.466ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.550m	20.304ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.450m	8.427ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.367m	347.466ms	1	1	100.00
V2	dma_abort	dma_abort	17.000s	1.272ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.750m	94.590ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	17.325us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	23.963us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	26.665us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	26.665us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	19.293us	1	1	100.00
		dma_csr_rw	1.000s	21.071us	1	1	100.00
		dma_csr_aliasing	6.000s	157.792us	1	1	100.00
		dma_same_csr_outstanding	2.000s	191.298us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	19.293us	1	1	100.00
		dma_csr_rw	1.000s	21.071us	1	1	100.00
		dma_csr_aliasing	6.000s	157.792us	1	1	100.00
		dma_same_csr_outstanding	2.000s	191.298us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	14.000s	303.375us	1	1	100.00
		dma_generic_stress	1.450m	8.427ms	1	1	100.00
		dma_handshake_stress	5.367m	347.466ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	261.082us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	224.211us	1	1	100.00
		dma_sec_cm	2.000s	36.725us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.367m	83.702ms	1	1	100.00
		dma_longer_transfer	3.000s	573.118us	1	1	100.00
		dma_stress_all_with_rand_reset	18.000s	1.066ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.115355934580474925268477495799624251212962606381329487592281818815598286572580
      Line 130, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1066091229ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1066091229ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---