EDN Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.910s	15.548us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.830s	25.568us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.940s	70.406us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.590s	118.216us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.380s	37.058us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.000s	39.014us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	70.406us	1	1	100.00
		edn_csr_aliasing	1.380s	37.058us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.070s	30.991us	1	1	100.00
V2	csrng_commands	edn_genbits	1.070s	30.991us	1	1	100.00
V2	genbits	edn_genbits	1.070s	30.991us	1	1	100.00
V2	interrupts	edn_intr	1.020s	23.247us	1	1	100.00
V2	alerts	edn_alert	0.990s	80.772us	1	1	100.00
V2	errs	edn_err	1.410s	19.201us	1	1	100.00
V2	disable	edn_disable	0.800s	34.142us	1	1	100.00
		edn_disable_auto_req_mode	1.170s	35.033us	1	1	100.00
V2	stress_all	edn_stress_all	3.850s	498.020us	1	1	100.00
V2	intr_test	edn_intr_test	0.810s	37.685us	1	1	100.00
V2	alert_test	edn_alert_test	0.900s	97.805us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.860s	175.148us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.860s	175.148us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.830s	25.568us	1	1	100.00
		edn_csr_rw	0.940s	70.406us	1	1	100.00
		edn_csr_aliasing	1.380s	37.058us	1	1	100.00
		edn_same_csr_outstanding	1.550s	39.343us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.830s	25.568us	1	1	100.00
		edn_csr_rw	0.940s	70.406us	1	1	100.00
		edn_csr_aliasing	1.380s	37.058us	1	1	100.00
		edn_same_csr_outstanding	1.550s	39.343us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.870s	657.825us	1	1	100.00
		edn_tl_intg_err	2.630s	145.761us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.270s	18.352us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.990s	80.772us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.870s	657.825us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.870s	657.825us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.870s	657.825us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.870s	657.825us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.990s	80.772us	1	1	100.00
		edn_sec_cm	3.870s	657.825us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.990s	80.772us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.630s	145.761us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	44.580s	43.944ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00