HMAC Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.120s 368.258us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.970s 19.918us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.710s 26.034us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.920s 6.322ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.420s 368.677us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.600s 390.657us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.710s 26.034us 1 1 100.00
hmac_csr_aliasing 4.420s 368.677us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 20.030s 1.598ms 1 1 100.00
V2 back_pressure hmac_back_pressure 45.730s 2.143ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.947m 22.617ms 1 1 100.00
hmac_test_sha384_vectors 21.270s 4.038ms 1 1 100.00
hmac_test_sha512_vectors 6.490m 25.391ms 1 1 100.00
hmac_test_hmac256_vectors 6.180s 770.048us 1 1 100.00
hmac_test_hmac384_vectors 6.270s 832.530us 1 1 100.00
hmac_test_hmac512_vectors 11.390s 464.724us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.000s 5.540ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.891m 5.322ms 1 1 100.00
V2 error hmac_error 0.690s 22.437us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 49.250s 14.331ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.120s 368.258us 1 1 100.00
hmac_long_msg 20.030s 1.598ms 1 1 100.00
hmac_back_pressure 45.730s 2.143ms 1 1 100.00
hmac_datapath_stress 5.891m 5.322ms 1 1 100.00
hmac_burst_wr 17.000s 5.540ms 1 1 100.00
hmac_stress_all 16.332m 16.982ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.120s 368.258us 1 1 100.00
hmac_long_msg 20.030s 1.598ms 1 1 100.00
hmac_back_pressure 45.730s 2.143ms 1 1 100.00
hmac_datapath_stress 5.891m 5.322ms 1 1 100.00
hmac_wipe_secret 49.250s 14.331ms 1 1 100.00
hmac_test_sha256_vectors 2.947m 22.617ms 1 1 100.00
hmac_test_sha384_vectors 21.270s 4.038ms 1 1 100.00
hmac_test_sha512_vectors 6.490m 25.391ms 1 1 100.00
hmac_test_hmac256_vectors 6.180s 770.048us 1 1 100.00
hmac_test_hmac384_vectors 6.270s 832.530us 1 1 100.00
hmac_test_hmac512_vectors 11.390s 464.724us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.120s 368.258us 1 1 100.00
hmac_long_msg 20.030s 1.598ms 1 1 100.00
hmac_back_pressure 45.730s 2.143ms 1 1 100.00
hmac_datapath_stress 5.891m 5.322ms 1 1 100.00
hmac_burst_wr 17.000s 5.540ms 1 1 100.00
hmac_error 0.690s 22.437us 1 1 100.00
hmac_wipe_secret 49.250s 14.331ms 1 1 100.00
hmac_test_sha256_vectors 2.947m 22.617ms 1 1 100.00
hmac_test_sha384_vectors 21.270s 4.038ms 1 1 100.00
hmac_test_sha512_vectors 6.490m 25.391ms 1 1 100.00
hmac_test_hmac256_vectors 6.180s 770.048us 1 1 100.00
hmac_test_hmac384_vectors 6.270s 832.530us 1 1 100.00
hmac_test_hmac512_vectors 11.390s 464.724us 1 1 100.00
hmac_stress_all 16.332m 16.982ms 1 1 100.00
V2 stress_all hmac_stress_all 16.332m 16.982ms 1 1 100.00
V2 alert_test hmac_alert_test 0.750s 19.250us 1 1 100.00
V2 intr_test hmac_intr_test 0.640s 55.562us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.140s 538.544us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.140s 538.544us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.970s 19.918us 1 1 100.00
hmac_csr_rw 0.710s 26.034us 1 1 100.00
hmac_csr_aliasing 4.420s 368.677us 1 1 100.00
hmac_same_csr_outstanding 1.050s 84.003us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.970s 19.918us 1 1 100.00
hmac_csr_rw 0.710s 26.034us 1 1 100.00
hmac_csr_aliasing 4.420s 368.677us 1 1 100.00
hmac_same_csr_outstanding 1.050s 84.003us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.880s 133.339us 1 1 100.00
hmac_tl_intg_err 2.880s 140.968us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.880s 140.968us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.120s 368.258us 1 1 100.00
V3 stress_reset hmac_stress_reset 0.850s 48.247us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.184m 87.676ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.210s 931.845us 1 1 100.00
TOTAL 28 28 100.00