I2C Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.850s	4.949ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	24.960s	2.340ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.740s	43.368us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.920s	59.668us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.140s	739.817us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.520s	130.349us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.270s	31.552us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.920s	59.668us	1	1	100.00
		i2c_csr_aliasing	1.520s	130.349us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.940s	28.807us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.760s	103.387us	0	1	0.00
V2	host_maxperf	i2c_host_perf	15.940s	6.381ms	1	1	100.00
V2	host_override	i2c_host_override	0.810s	34.671us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.480m	5.191ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	32.040s	1.945ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.040s	515.173us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.690s	422.690us	1	1	100.00
		i2c_host_fifo_reset_rx	3.590s	1.031ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.889m	9.671ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.150s	1.953ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.870s	422.923us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.210s	1.207ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	21.320s	5.838ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.920s	1.013ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	7.150s	1.312ms	1	1	100.00
		i2c_target_intr_smoke	5.920s	2.577ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.230s	1.244ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.260s	211.570us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.012m	25.199ms	1	1	100.00
		i2c_target_stress_rd	7.150s	1.312ms	1	1	100.00
		i2c_target_intr_stress_wr	26.040s	24.210ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.690s	6.217ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.420s	252.619us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.430s	1.403ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.710s	3.787ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.550s	668.264us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.340s	165.266us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	15.940s	6.381ms	1	1	100.00
		i2c_host_perf_precise	1.910s	489.517us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.150s	1.953ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.790s	337.764us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.680s	434.526us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.020s	563.754us	1	1	100.00
		i2c_target_nack_txstretch	1.080s	483.324us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	1.490s	999.538us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.980s	1.606ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.660s	16.398us	1	1	100.00
V2	intr_test	i2c_intr_test	0.800s	33.617us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.080s	143.532us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.080s	143.532us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.740s	43.368us	1	1	100.00
		i2c_csr_rw	0.920s	59.668us	1	1	100.00
		i2c_csr_aliasing	1.520s	130.349us	1	1	100.00
		i2c_same_csr_outstanding	1.080s	63.277us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.740s	43.368us	1	1	100.00
		i2c_csr_rw	0.920s	59.668us	1	1	100.00
		i2c_csr_aliasing	1.520s	130.349us	1	1	100.00
		i2c_same_csr_outstanding	1.080s	63.277us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.340s	161.134us	1	1	100.00
		i2c_sec_cm	0.840s	160.853us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.340s	161.134us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.900s	298.438us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.050s	394.740us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.200s	1.608ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.41628450031337818461216100130851951174640520793218778471659018417487170800100
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  28807413 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  28807413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.95983324858338308439596980141525575660034625569175165757241884499880133550585
      Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 103387194 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 103387194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.87195559623707669156627274177956361270960989143340538313299840680413030058231
      Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1608422178 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1608422178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.50873528103738546684805045921094724656658334435698966225688241782708381317590
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1207198862 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1207198862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.83065254548179124519741889455463217954886594162123402890410838405235429026749
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 394740360 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 394740360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.83930166930791999778961224004191877479341400796801328878335564521890156438510
      Line 120, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 298437950 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 298437950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.38791511254591015207571583592248184500309652692736679491775021617088396676400
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 422922811 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @42912
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.83854940238258108114579859065916455958945502093003606085046134580642588613361
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 483324132 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 483324132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---