KEYMGR Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.020s	1.457ms	1	1	100.00
V1	random	keymgr_random	2.760s	154.880us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.050s	76.746us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.930s	11.309us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.050s	878.258us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.310s	135.886us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.530s	31.531us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.930s	11.309us	1	1	100.00
		keymgr_csr_aliasing	3.310s	135.886us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.260s	142.604us	1	1	100.00
V2	sideload	keymgr_sideload	1.410s	72.976us	1	1	100.00
		keymgr_sideload_kmac	2.730s	179.776us	1	1	100.00
		keymgr_sideload_aes	1.910s	34.588us	1	1	100.00
		keymgr_sideload_otbn	2.850s	74.410us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.770s	51.144us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.980s	122.411us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.500s	51.289us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	8.620s	610.246us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.340s	53.135us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.690s	161.565us	1	1	100.00
V2	stress_all	keymgr_stress_all	6.160s	316.776us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.820s	22.444us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.820s	30.248us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.480s	585.991us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.480s	585.991us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.050s	76.746us	1	1	100.00
		keymgr_csr_rw	0.930s	11.309us	1	1	100.00
		keymgr_csr_aliasing	3.310s	135.886us	1	1	100.00
		keymgr_same_csr_outstanding	1.300s	88.032us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.050s	76.746us	1	1	100.00
		keymgr_csr_rw	0.930s	11.309us	1	1	100.00
		keymgr_csr_aliasing	3.310s	135.886us	1	1	100.00
		keymgr_same_csr_outstanding	1.300s	88.032us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
		keymgr_tl_intg_err	4.730s	221.555us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.830s	695.190us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.830s	695.190us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.830s	695.190us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.830s	695.190us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.220s	1.888ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.730s	221.555us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.830s	695.190us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.260s	142.604us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.760s	154.880us	1	1	100.00
		keymgr_csr_rw	0.930s	11.309us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.760s	154.880us	1	1	100.00
		keymgr_csr_rw	0.930s	11.309us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.760s	154.880us	1	1	100.00
		keymgr_csr_rw	0.930s	11.309us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.980s	122.411us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.340s	53.135us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.340s	53.135us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.760s	154.880us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	12.510s	609.798us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.700s	499.574us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.980s	122.411us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.700s	499.574us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.700s	499.574us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.700s	499.574us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.150s	9.005ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.700s	499.574us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.110s	120.918us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.39813264122496824839853441200795083457548713328298061656775585088909631848497
      Line 163, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 120917893 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 120917893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---