SPI_DEVICE/1R1W Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.377m	48.992ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.840s	79.387us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.030s	35.444us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.890s	2.096ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.850s	1.381ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.680s	124.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.030s	35.444us	1	1	100.00
		spi_device_csr_aliasing	5.850s	1.381ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	14.351us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.190s	285.242us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.800s	18.583us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.880s	4.132us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.830s	6.430us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	7.080s	804.349us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	7.080s	804.349us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.320s	1.839ms	1	1	100.00
		spi_device_tpm_sts_read	0.840s	48.157us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.140s	16.909ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.380s	3.833ms	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.470s	611.233us	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.470s	611.233us	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.740s	3.592ms	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.740s	3.592ms	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.740s	3.592ms	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.740s	3.592ms	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.740s	3.592ms	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.020s	9.667ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.640s	247.947us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.640s	247.947us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.640s	247.947us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.760s	492.684us	1	1	100.00
		spi_device_read_buffer_direct	2.850s	130.639us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.640s	247.947us	1	1	100.00
		spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	14.710s	1.006ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.550s	118.330us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.550s	118.330us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.377m	48.992ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	34.400s	3.679ms	1	1	100.00
V2	stress_all	spi_device_stress_all	0.870s	75.517us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.760s	15.775us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.850s	43.938us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.670s	67.645us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.670s	67.645us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.840s	79.387us	1	1	100.00
		spi_device_csr_rw	1.030s	35.444us	1	1	100.00
		spi_device_csr_aliasing	5.850s	1.381ms	1	1	100.00
		spi_device_same_csr_outstanding	1.660s	503.471us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.840s	79.387us	1	1	100.00
		spi_device_csr_rw	1.030s	35.444us	1	1	100.00
		spi_device_csr_aliasing	5.850s	1.381ms	1	1	100.00
		spi_device_same_csr_outstanding	1.660s	503.471us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.120s	207.655us	1	1	100.00
		spi_device_tl_intg_err	5.720s	295.369us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.720s	295.369us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.070s	26.530us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.65020673972591141007884300541110570277596377118343874932384674093584171677508
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3381854 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[9])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3381854 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3381854 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.39846181111567828886659405617958822327888361756456817186461314334405862678945
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4154790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd78cd2 [110101111000110011010010] vs 0x0 [0])
        UVM_ERROR @   4199790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x901518 [100100000001010100011000] vs 0x0 [0])
        UVM_ERROR @   4269790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcb4b34 [110010110100101100110100] vs 0x0 [0])
        UVM_ERROR @   4343790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1ee4e3 [111101110010011100011] vs 0x0 [0])
        UVM_ERROR @   4353790 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5513ad [10101010001001110101101] vs 0x0 [0])