SPI_HOST Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.000s	291.595us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	17.357us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	81.116us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	326.092us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	125.598us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	45.356us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	81.116us	1	1	100.00
		spi_host_csr_aliasing	2.000s	125.598us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	16.256us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	19.010us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	7.000s	68.475us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	275.343us	1	1	100.00
		spi_host_error_cmd	1.000s	31.492us	1	1	100.00
		spi_host_event	19.000s	660.029us	1	1	100.00
V2	clock_rate	spi_host_speed	11.000s	780.779us	1	1	100.00
V2	speed	spi_host_speed	11.000s	780.779us	1	1	100.00
V2	chip_select_timing	spi_host_speed	11.000s	780.779us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	86.421us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	84.366us	1	1	100.00
V2	cpol_cpha	spi_host_speed	11.000s	780.779us	1	1	100.00
V2	full_cycle	spi_host_speed	11.000s	780.779us	1	1	100.00
V2	duplex	spi_host_smoke	11.000s	291.595us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	11.000s	291.595us	1	1	100.00
V2	stress_all	spi_host_stress_all	10.000s	625.826us	1	1	100.00
V2	spien	spi_host_spien	5.000s	1.931ms	1	1	100.00
V2	stall	spi_host_status_stall	34.000s	2.123ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	136.779us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	275.343us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	35.243us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	45.465us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	130.814us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	130.814us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	17.357us	1	1	100.00
		spi_host_csr_rw	1.000s	81.116us	1	1	100.00
		spi_host_csr_aliasing	2.000s	125.598us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	17.851us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	17.357us	1	1	100.00
		spi_host_csr_rw	1.000s	81.116us	1	1	100.00
		spi_host_csr_aliasing	2.000s	125.598us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	17.851us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	101.337us	1	1	100.00
		spi_host_sec_cm	1.000s	72.184us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	101.337us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	22.000s	1.685ms	1	1	100.00
		TOTAL			26	26	100.00