SRAM_CTRL/MAIN Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.420s	783.766us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	41.837us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	12.013us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.670s	765.835us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	20.894us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.100s	1.367ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	12.013us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	20.894us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.884m	30.773ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	58.720s	2.655ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.702m	56.956ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.286m	10.192ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	23.926m	218.150ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	56.920s	4.778ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	48.310s	26.150ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.340m	40.218ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.840s	520.394us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.573m	29.413ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	20.010s	1.483ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.590s	2.508ms	1	1	100.00
		sram_ctrl_throughput_w_readback	15.820s	4.935ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.720m	1.720ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.170s	1.335ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.235h	257.940ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.630s	32.028us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.270s	571.640us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.270s	571.640us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	41.837us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	12.013us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	20.894us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	93.272us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	41.837us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	12.013us	1	1	100.00
		sram_ctrl_csr_aliasing	0.730s	20.894us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	93.272us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	30.240s	7.532ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.610s	13.814us	0	1	0.00
		sram_ctrl_tl_intg_err	1.270s	102.871us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.610s	13.814us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.270s	102.871us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.720m	1.720ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.720m	1.720ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	12.013us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.340m	40.218ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.340m	40.218ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.340m	40.218ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	48.310s	26.150ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.700s	3.178ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	30.240s	7.532ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.350s	3.492ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.420s	783.766us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.420s	783.766us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.340m	40.218ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.610s	13.814us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	48.310s	26.150ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.610s	13.814us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.610s	13.814us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.420s	783.766us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.610s	13.814us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.130s	2.095ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.22977686980559439270034608017360460272577969975571676526994713876118908266662
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  13813896 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  13813896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---