SRAM_CTRL/RET Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.510s	267.842us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.870s	44.063us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	15.766us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.680s	1.194ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.650s	13.392us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.930s	119.275us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	15.766us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	13.392us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.940s	138.387us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.080s	195.453us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.963m	12.686ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.303m	16.886ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	1.032m	22.589ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.486m	15.568ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.280s	79.783us	1	1	100.00
V2	executable	sram_ctrl_executable	6.350m	7.191ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.340s	214.038us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.192m	140.205ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	8.330s	80.572us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.110s	61.879us	1	1	100.00
		sram_ctrl_throughput_w_readback	34.250s	269.451us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.203m	5.661ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.920s	85.521us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	13.263m	22.170ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.620s	15.654us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.560s	21.833us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.560s	21.833us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.870s	44.063us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	15.766us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	13.392us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.690s	20.383us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.870s	44.063us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	15.766us	1	1	100.00
		sram_ctrl_csr_aliasing	0.650s	13.392us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.690s	20.383us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.210s	1.441ms	0	1	0.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.630s	20.926us	0	1	0.00
		sram_ctrl_tl_intg_err	1.890s	313.449us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.630s	20.926us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.890s	313.449us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.203m	5.661ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.203m	5.661ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	15.766us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.350m	7.191ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.350m	7.191ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.350m	7.191ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.280s	79.783us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.890s	202.868us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.210s	1.441ms	0	1	0.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.090s	65.844us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.510s	267.842us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.510s	267.842us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.350m	7.191ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.630s	20.926us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.280s	79.783us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.630s	20.926us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.630s	20.926us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.510s	267.842us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.630s	20.926us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	44.920s	899.068us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.19100204294155343201948930303952980758756269990690769222960569902206860791755
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 202868156 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 202868156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.19778887340729539785935912167932765569259437798825174110133993764358825390004
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  20926288 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  20926288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

    • 0.sram_ctrl_passthru_mem_tl_intg_err.21284306080743642403127588302477194348452512080692618958335016543070123910947
      Line 147, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_ERROR @ 1441085912 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1441085912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---