UART Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: 80590e0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.440s	291.010us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.850s	43.620us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.700s	19.457us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.790s	337.180us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.030s	135.273us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.580s	104.926us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.700s	19.457us	1	1	100.00
		uart_csr_aliasing	1.030s	135.273us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	14.410s	32.838ms	1	1	100.00
V2	parity	uart_smoke	1.440s	291.010us	1	1	100.00
		uart_tx_rx	14.410s	32.838ms	1	1	100.00
V2	parity_error	uart_intr	8.530s	21.446ms	1	1	100.00
		uart_rx_parity_err	40.490s	128.491ms	1	1	100.00
V2	watermark	uart_tx_rx	14.410s	32.838ms	1	1	100.00
		uart_intr	8.530s	21.446ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.203m	114.684ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	13.950s	226.416ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	10.330s	93.169ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.530s	21.446ms	1	1	100.00
V2	rx_break_err	uart_intr	8.530s	21.446ms	1	1	100.00
V2	rx_timeout	uart_intr	8.530s	21.446ms	1	1	100.00
V2	perf	uart_perf	5.438m	11.856ms	1	1	100.00
V2	sys_loopback	uart_loopback	18.270s	12.776ms	1	1	100.00
V2	line_loopback	uart_loopback	18.270s	12.776ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	43.920s	60.991ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.710s	1.639ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.840s	1.353ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.460s	3.800ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.163m	90.051ms	1	1	100.00
V2	stress_all	uart_stress_all	19.860s	18.367ms	0	1	0.00
V2	alert_test	uart_alert_test	0.710s	13.965us	1	1	100.00
V2	intr_test	uart_intr_test	0.860s	12.851us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.830s	442.435us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.830s	442.435us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.850s	43.620us	1	1	100.00
		uart_csr_rw	0.700s	19.457us	1	1	100.00
		uart_csr_aliasing	1.030s	135.273us	1	1	100.00
		uart_same_csr_outstanding	0.820s	102.712us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.850s	43.620us	1	1	100.00
		uart_csr_rw	0.700s	19.457us	1	1	100.00
		uart_csr_aliasing	1.030s	135.273us	1	1	100.00
		uart_same_csr_outstanding	0.820s	102.712us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	0.920s	110.644us	1	1	100.00
		uart_tl_intg_err	1.670s	410.756us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.670s	410.756us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.430s	2.247ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.33325517848887472223528309738579437800603945461646812470735469526504278405872
      Line 80, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 60968060599 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 60971938119 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 60973489127 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 60973489127 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 60974121775 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.74822334487371881419502728386483902009137808503806061798539189183317834200707
      Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 16504476695 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 16506196695 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 16553266695 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 16561626695 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 16562246695 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0