CHIP Simulation Results

Tuesday November 04 2025 16:01:43 UTC

GitHub Revision: `80590e0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.834m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.834m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.255m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	42.109s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	56.187s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.319m	282.620us	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.319m	282.620us	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.319m	282.620us	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	29.820s	10.180us	0	1	0.00
		chip_sw_example_manufacturer	2.369m		0	1	0.00
		chip_sw_example_concurrency	3.337m	150.381us	1	1	100.00
		chip_sw_uart_smoketest_signed	9.849s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.550s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.590s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.590s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.750s	12.344us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.467m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	35.836m	3.178ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.790m	262.484us	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	22.113s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.653s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	21.014s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	23.988s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.320s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.320s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.983m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.833m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.306m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.306m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.262m	117.017us	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.267m	117.022us	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.873m	272.410us	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.803s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.681s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.603m	375.175us	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.894m	248.731us	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.825m	461.546us	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.825m	461.546us	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.259s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.022m	164.303us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.022m	164.303us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.770m	2.271ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.004m	146.381us	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.213m	225.683us	1	1	100.00
		chip_sw_aes_idle	3.083m	147.260us	1	1	100.00
		chip_sw_hmac_enc_idle	3.725m	161.528us	1	1	100.00
		chip_sw_kmac_idle	3.134m	145.019us	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.635m	165.664us	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	3.076m	165.664us	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	3.404m	165.600us	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	3.390m	165.712us	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.370s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.534s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.934s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.638s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.946s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.234s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.359s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.370s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.534s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.934s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.638s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.946s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.234s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.359s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	36.790s	10.260us	0	1	0.00
		chip_sw_aes_enc_jitter_en	37.940s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.710s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.880s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.340s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.454s		0	1	0.00
		chip_sw_clkmgr_jitter	3.035m	141.903us	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	6.626m	1.779ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	37.560s	10.100us	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	36.550s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	36.820s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	40.330s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	38.060s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	40.060s	10.240us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.395s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.926s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.889s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.445s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.671m	921.911us	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.777m	495.530us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.022m	164.303us	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.569s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.777m	495.530us	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.471s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.233s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.739s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.428s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.325s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.671m	921.911us	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.873m	272.410us	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	6.992m	375.424us	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.137m	267.324us	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	6.981m	317.997us	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.139m	144.086us	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.671m	921.911us	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.039s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.795s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.671m	921.911us	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	9.382s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	6.981m	317.997us	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.054s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.371s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.518s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	9.466s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	9.312s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.054s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.795s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	28.210s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.257m	268.076us	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.222s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.327s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.648s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	9.987s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.523m	268.196us	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	13.469m	1.275ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.465s		0	1	0.00
		chip_prim_tl_access	12.707m	971.002us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.370s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.534s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.934s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.638s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.946s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.234s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.359s		0	1	0.00
		chip_rv_dm_lc_disabled	4.603m	375.175us	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.245m	157.124us	1	1	100.00
		chip_sw_aes_enc_jitter_en	37.940s	10.260us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.047m	145.826us	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.083m	147.260us	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.539m	156.418us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.710s	10.180us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.725m	161.528us	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.727m	148.942us	1	1	100.00
		chip_sw_kmac_mode_kmac	3.492m	172.126us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.340s	10.380us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.523m	268.196us	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	31.510s	10.120us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.750m	212.516us	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.134m	145.019us	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	6.390m	247.901us	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	6.390m	247.901us	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.021s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.206m	156.785us	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	10.737s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.523m	268.196us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.880s	10.280us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	40.978m	1.470ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	36.790s	10.260us	0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.213m	225.683us	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.213m	225.683us	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.213m	225.683us	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.862m	264.791us	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.469m	1.275ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.469m	1.275ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.921m	314.082us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.454s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.465s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.671m	921.911us	1	1	100.00
		chip_sw_data_integrity_escalation	2.306m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.862m	264.791us	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.523m	268.196us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.921m	314.082us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.171m	167.837us	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.862m	264.791us	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.523m	268.196us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	5.921m	314.082us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.171m	167.837us	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	9.935s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	28.210s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.222s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.327s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.648s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	9.987s		0	1	0.00
		chip_sw_lc_ctrl_transition	10.193s		0	1	0.00
		chip_prim_tl_access	12.707m	971.002us	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.707m	971.002us	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.269s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	10.167s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.926s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	36.790s	10.260us	0	1	0.00
		chip_sw_aes_enc_jitter_en	37.940s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.710s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	36.880s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.340s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.454s		0	1	0.00
		chip_sw_clkmgr_jitter	3.035m	141.903us	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	2.834m	137.312us	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	2.834m	137.312us	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.483m	155.088us	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	2.875m	138.803us	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.796m	167.944us	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.835m	251.574us	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.088m	180.154us	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.384m	164.781us	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.171m	167.837us	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	6.992m	375.424us	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	6.992m	375.424us	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	2.716m	157.108us	1	1	100.00
		chip_sw_aon_timer_smoketest	2.990m	163.251us	1	1	100.00
		chip_sw_clkmgr_smoketest	2.392m	142.963us	1	1	100.00
		chip_sw_csrng_smoketest	2.475m	144.800us	1	1	100.00
		chip_sw_gpio_smoketest	2.679m	165.762us	1	1	100.00
		chip_sw_hmac_smoketest	3.261m	182.022us	1	1	100.00
		chip_sw_kmac_smoketest	3.008m	171.089us	1	1	100.00
		chip_sw_otbn_smoketest	3.255m	182.378us	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.399m	148.072us	1	1	100.00
		chip_sw_rv_plic_smoketest	2.420m	145.084us	1	1	100.00
		chip_sw_rv_timer_smoketest	3.340m	248.732us	1	1	100.00
		chip_sw_rstmgr_smoketest	2.397m	141.630us	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.446m	145.484us	1	1	100.00
		chip_sw_uart_smoketest	2.550m	155.761us	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.486s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	9.849s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.467m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	10.702s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.725m	207.724us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.394m	231.539us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.414m	221.130us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.554m	217.465us	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.841s		0	1	0.00
		chip_rv_dm_lc_disabled	4.603m	375.175us	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.250s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.169s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	20.079s		0	1	0.00
		chip_sw_lc_walkthrough_rma	9.773s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.841s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	9.787m	602.412us	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.521m	764.957us	1	1	100.00
		rom_volatile_raw_unlock	10.351s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.014s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.156m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.482m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.035m	118.273us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.035m	118.273us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.590s		0	1	0.00
		chip_same_csr_outstanding	11.480s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.590s		0	1	0.00
		chip_same_csr_outstanding	11.480s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.181m	60.366us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.980s	11.653us	1	1	100.00
		xbar_smoke_large_delays	5.579m	2.665ms	1	1	100.00
		xbar_smoke_slow_rsp	5.902m	1.946ms	1	1	100.00
		xbar_random_zero_delays	36.370s	33.537us	1	1	100.00
		xbar_random_large_delays	2.495m	1.209ms	1	1	100.00
		xbar_random_slow_rsp	33.135m	11.749ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	9.560s	8.088us	1	1	100.00
		xbar_error_and_unmapped_addr	1.016m	92.811us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.327m	211.702us	1	1	100.00
		xbar_error_and_unmapped_addr	1.016m	92.811us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.406m	652.135us	1	1	100.00
		xbar_access_same_device_slow_rsp	27.202m	9.474ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	57.270s	145.410us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.498m	263.951us	1	1	100.00
		xbar_stress_all_with_error	13.583m	1.810ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.370m	166.303us	1	1	100.00
		xbar_stress_all_with_reset_error	2.324m	106.329us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.496s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.951s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.116s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.002s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.894s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.513s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.699s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	9.740s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.519s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	9.928s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	9.323s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.847s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	9.683s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.004m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.124m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.153m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.214m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.151m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	47.619s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.137m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	55.458s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	56.551s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	46.616s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	52.130s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	48.898s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.727s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	31.006s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	29.974s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	10.907s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.569s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.313s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	10.645s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.620s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	9.515s		0	1	0.00
		rom_e2e_asm_init_dev	12.201s		0	1	0.00
		rom_e2e_asm_init_prod	9.583s		0	1	0.00
		rom_e2e_asm_init_prod_end	9.726s		0	1	0.00
		rom_e2e_asm_init_rma	10.618s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	9.525s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	9.549s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	9.887s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	9.849s		0	1	0.00
V2		TOTAL			69	205	33.66
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.006m	165.756us	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.868m	137.323us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.192s		0	1	0.00
		rom_e2e_jtag_debug_dev	9.612s		0	1	0.00
		rom_e2e_jtag_debug_rma	9.956s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.595s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.671m	921.911us	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.153s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.877m	158.780us	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	10.648s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	9.476s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.192s		0	1	0.00
		rom_e2e_jtag_debug_dev	9.612s		0	1	0.00
		rom_e2e_jtag_debug_rma	9.956s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	9.504s		0	1	0.00
		rom_e2e_jtag_inject_dev	9.349s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.119s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.446s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.637m	922.024us	1	1	100.00
		chip_sw_entropy_src_kat_test	2.988m	144.305us	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.700m	141.524us	1	1	100.00
		chip_plic_all_irqs_0	7.813m	351.661us	1	1	100.00
		chip_plic_all_irqs_10	8.848m	382.901us	1	1	100.00
		chip_sw_dma_inline_hashing	3.258m	188.442us	1	1	100.00
		chip_sw_dma_abort	3.367m	161.256us	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	9.618s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	9.780s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.979s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	9.804s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.672s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	9.797s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.216s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.483s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.504s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.717s		0	1	0.00
		chip_sw_entropy_src_smoketest	3.399m	187.208us	1	1	100.00
		chip_sw_mbx_smoketest	4.546m	300.987us	1	1	100.00
		TOTAL			82	250	32.80

Failure Buckets

Job returned non-zero exit code has 130 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.9983545434240103729181073733186282873194785458491774875288266739346667555556
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.217s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.101348322859052832493825245589225393335721046549604928981413907779302729822868
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.227s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.11527598719313800077755359863334932618184967592772325024675328398123428963820
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.206s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.15050117156413352357249153860757744873525974505256739960565146944450863663340
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 101.260s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.32272822370030176750359168262375907441919926145051856487067937899278477278186
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 101.211s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 125 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:
- Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.
  - 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.69146164091025025791252763461779321424210033347605646873200928225419154833736
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.39784368654082902231860701591018262168200352666028160845548651070387607436015
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.74044442171423656587553829639837956466021593681640979666237983655572882310099
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.97653913890961463786119715280738288275208068474299377155619270149124624266950
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.55150559147114906781011782820342811654231093929000549881689062049723950952059
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 5 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.109877742356276511305447796020180054536276438071518566212176804937605872602465
    Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 375.424000 us: (pwrmgr_rstreqs_sva_if.sv:54) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 375.424000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.98079148769301201888308102357250864075127559351060935366057869911740489294026
    Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:54) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.64700243573517679635577354713870470002596209212738073573015959947115784045936
    Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:54) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.60381662334508450750601658446861045536246497380987583965011113846102142904343
    Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.600000 us: (pwrmgr_rstreqs_sva_if.sv:54) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.600000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.49347331820807812709586920506635089627040604121314419200227469051625079285916
    Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.712000 us: (pwrmgr_rstreqs_sva_if.sv:54) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.712000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.16288008703410256846290880325734395305324281443081390999915361712279385659237
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.30944848134856580755832458491710169246057601085113331056267151205286814351088
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.99685226089195375616419038088596605167948395047989788159430790930317720284987
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.23255210136125124276615196792782918152543385447088186772902261735883405603193
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 268.196000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1864164495420811348631056781362078714923954050674793434003295423142535188149525762654550579082845817818078630414647040643089429743349915958174030860999772 [0x2397d8a3aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a5c168527f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.196000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.67229620200507749198790175630310489673822602126937067580422570177848063978470
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 268.076000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7124852616503399652436718934960364071847533953507508898258889166252356107205123657209139030747396104308952507375915363575533847724993881872844753060846684 [0x88098ddcaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd30e5f3d2d7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.076000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.102540070529382937601895880687505060754847847067983708081771481194712960803482
Line 6256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 117.017000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: 'h30480000  a_data: 'h4d449f3f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h0  a_user: 'h2697c  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.017000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.27721887169877214229222740075724853404113936708645970290929838779149149720481
Line 6256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 117.022000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: 'h30480000  a_data: 'h24487249  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h0  a_user: 'h26941  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.022000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.38187598696700741077919732115254292080430594570042818539217713161453748013879
    Line 529, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.91297538793937223614245782175843231384058379160083891200147966823915890467952
    Line 418, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 262.484000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 262.484000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.106240458697102803218467758501392122406397736103829638479660187531637543083434
    Line 433, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 158.780000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 158.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.31773608154817479299695420777929039422068934201949079823610156349910728250960
    Line 635, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 317.997000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 317.997000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.80748491747873845160467278875924666458737564563825780621120129218445030506266
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
  UVM_ERROR @ 137.312000 us: (chip_sw_soc_proxy_smoke_vseq.sv:52) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
  UVM_INFO @ 137.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.60248880777607108774785634559320166630115704957634861131791463498766512928121
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 155.088000 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 155.088000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.2978068576681288099838098015149323448961467022371494270834327786493151206784
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 138.803000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 138.803000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.35796349618540995554022940279271835506502505038851299288762907010587725471920
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 461.546000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3168 usec which is not in the range 289 usec and 334 usec
  UVM_INFO @ 461.546000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.80317945764236545194023720455203520348336672279337609637023723937167651610320
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 164.303000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 164.303000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.86401926519476580430224447125372097089684413461503033351548878711641579745509
    Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 251.574000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 251.574000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.86664570146916047164646426988720861671344074270320494895529511918198570722503
    Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.102829546138185592840090941581787069525147083868460229603872441894284726079804
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 118.273000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 118.273000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.7361963591976061532428983502523721947472506890234098649225217622793095732608
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 375.175000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40748 read out mismatch
  UVM_INFO @ 375.175000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.10928141848374706240100041818990659758942963381429787501299390749726469445970
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.9913430911976042914288544207307335457555207882004219911848221270611809360101
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 161.256000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 161.256000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```