AES/MASKED Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	119.491us	1	1	100.00
V1	smoke	aes_smoke	2.000s	181.389us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.000s	56.952us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	84.242us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	333.091us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	179.972us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	264.362us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	84.242us	1	1	100.00
		aes_csr_aliasing	2.000s	179.972us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	181.389us	1	1	100.00
		aes_config_error	3.000s	85.702us	1	1	100.00
		aes_stress	4.000s	160.034us	1	1	100.00
V2	key_length	aes_smoke	2.000s	181.389us	1	1	100.00
		aes_config_error	3.000s	85.702us	1	1	100.00
		aes_stress	4.000s	160.034us	1	1	100.00
V2	back2back	aes_stress	4.000s	160.034us	1	1	100.00
		aes_b2b	16.000s	317.301us	1	1	100.00
V2	backpressure	aes_stress	4.000s	160.034us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	181.389us	1	1	100.00
		aes_config_error	3.000s	85.702us	1	1	100.00
		aes_stress	4.000s	160.034us	1	1	100.00
		aes_alert_reset	2.000s	133.294us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	81.076us	1	1	100.00
		aes_config_error	3.000s	85.702us	1	1	100.00
		aes_alert_reset	2.000s	133.294us	1	1	100.00
V2	trigger_clear_test	aes_clear	7.000s	131.625us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	294.125us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	133.294us	1	1	100.00
V2	stress	aes_stress	4.000s	160.034us	1	1	100.00
V2	sideload	aes_stress	4.000s	160.034us	1	1	100.00
		aes_sideload	2.000s	110.802us	1	1	100.00
V2	deinitialization	aes_deinit	4.000s	115.139us	1	1	100.00
V2	stress_all	aes_stress_all	47.000s	5.654ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	53.725us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	635.292us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	635.292us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.000s	56.952us	1	1	100.00
		aes_csr_rw	2.000s	84.242us	1	1	100.00
		aes_csr_aliasing	2.000s	179.972us	1	1	100.00
		aes_same_csr_outstanding	2.000s	125.244us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.000s	56.952us	1	1	100.00
		aes_csr_rw	2.000s	84.242us	1	1	100.00
		aes_csr_aliasing	2.000s	179.972us	1	1	100.00
		aes_same_csr_outstanding	2.000s	125.244us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	64.391us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	84.678us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	84.678us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	84.678us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	84.678us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	477.748us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	3.000s	750.325us	1	1	100.00
		aes_tl_intg_err	2.000s	127.513us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	127.513us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	133.294us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	84.678us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	181.389us	1	1	100.00
		aes_stress	4.000s	160.034us	1	1	100.00
		aes_alert_reset	2.000s	133.294us	1	1	100.00
		aes_core_fi	3.000s	154.153us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	84.678us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	62.969us	1	1	100.00
		aes_stress	4.000s	160.034us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	160.034us	1	1	100.00
		aes_sideload	2.000s	110.802us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	62.969us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	62.969us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	62.969us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	62.969us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	62.969us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	160.034us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	160.034us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	149.699us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
		aes_ctr_fi	2.000s	75.487us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	149.699us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	54.262us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	149.699us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_ctr_fi	2.000s	75.487us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
		aes_ctr_fi	2.000s	75.487us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	133.294us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
		aes_ctr_fi	2.000s	75.487us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
		aes_ctr_fi	2.000s	75.487us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_ctr_fi	2.000s	75.487us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	149.699us	1	1	100.00
		aes_control_fi	2.000s	52.702us	1	1	100.00
		aes_cipher_fi	2.000s	54.262us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.000s	712.190us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.94798213710133371273636058092294971751614714478970886848241241693389314085937
      Line 275, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 712189573 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 712189573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---