DMA Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	657.006us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	1.811ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	674.656us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	15.775us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	17.523us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	293.964us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	2.157ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	23.038us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	17.523us	1	1	100.00
		dma_csr_aliasing	7.000s	2.157ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	29.000s	37.992ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	8.767m	97.406ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1.383m	11.622ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.383m	11.622ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	8.767m	97.406ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	7.633m	191.566ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.383m	11.622ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	635.880us	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.600m	50.504ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	13.928us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	14.013us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	109.075us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	109.075us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	15.775us	1	1	100.00
		dma_csr_rw	2.000s	17.523us	1	1	100.00
		dma_csr_aliasing	7.000s	2.157ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	175.954us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	15.775us	1	1	100.00
		dma_csr_rw	2.000s	17.523us	1	1	100.00
		dma_csr_aliasing	7.000s	2.157ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	175.954us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	19.000s	74.133us	1	1	100.00
		dma_generic_stress	7.633m	191.566ms	1	1	100.00
		dma_handshake_stress	1.383m	11.622ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	660.401us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	180.227us	1	1	100.00
		dma_sec_cm	2.000s	36.181us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	55.000s	6.109ms	1	1	100.00
		dma_longer_transfer	1.100m	14.794ms	1	1	100.00
		dma_stress_all_with_rand_reset	5.000s	277.237us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.27031711072940875699882638587997931446685456228563529561272906443235669579659
      Line 96, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  277236622ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  277236622ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---