EDN Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.010s 17.039us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.790s 28.245us 1 1 100.00
V1 csr_rw edn_csr_rw 0.790s 14.402us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.240s 117.574us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.940s 47.763us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.700s 61.614us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.790s 14.402us 1 1 100.00
edn_csr_aliasing 0.940s 47.763us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 3.110s 333.030us 1 1 100.00
V2 csrng_commands edn_genbits 3.110s 333.030us 1 1 100.00
V2 genbits edn_genbits 3.110s 333.030us 1 1 100.00
V2 interrupts edn_intr 1.000s 90.312us 1 1 100.00
V2 alerts edn_alert 1.040s 28.979us 1 1 100.00
V2 errs edn_err 0.900s 21.264us 1 1 100.00
V2 disable edn_disable 0.830s 22.618us 1 1 100.00
edn_disable_auto_req_mode 1.090s 64.760us 1 1 100.00
V2 stress_all edn_stress_all 4.480s 316.318us 1 1 100.00
V2 intr_test edn_intr_test 0.870s 15.969us 1 1 100.00
V2 alert_test edn_alert_test 0.920s 18.314us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.720s 372.478us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.720s 372.478us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.790s 28.245us 1 1 100.00
edn_csr_rw 0.790s 14.402us 1 1 100.00
edn_csr_aliasing 0.940s 47.763us 1 1 100.00
edn_same_csr_outstanding 0.960s 18.693us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.790s 28.245us 1 1 100.00
edn_csr_rw 0.790s 14.402us 1 1 100.00
edn_csr_aliasing 0.940s 47.763us 1 1 100.00
edn_same_csr_outstanding 0.960s 18.693us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.190s 562.049us 1 1 100.00
edn_tl_intg_err 1.880s 94.189us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.350s 22.752us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.040s 28.979us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.190s 562.049us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.190s 562.049us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.190s 562.049us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.190s 562.049us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.040s 28.979us 1 1 100.00
edn_sec_cm 6.190s 562.049us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.040s 28.979us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.880s 94.189us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets