HMAC Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.470s 650.738us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.890s 164.227us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.640s 37.290us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.500s 1.315ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.090s 397.828us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.080s 32.648us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.640s 37.290us 1 1 100.00
hmac_csr_aliasing 4.090s 397.828us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 3.890s 496.207us 1 1 100.00
V2 back_pressure hmac_back_pressure 7.170s 154.687us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.070s 729.740us 1 1 100.00
hmac_test_sha384_vectors 6.303m 11.213ms 1 1 100.00
hmac_test_sha512_vectors 18.710s 823.669us 1 1 100.00
hmac_test_hmac256_vectors 6.180s 202.477us 1 1 100.00
hmac_test_hmac384_vectors 6.390s 204.997us 1 1 100.00
hmac_test_hmac512_vectors 10.380s 345.697us 1 1 100.00
V2 burst_wr hmac_burst_wr 5.190s 528.904us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 22.023m 8.465ms 1 1 100.00
V2 error hmac_error 3.370s 329.648us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.008m 20.656ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.470s 650.738us 1 1 100.00
hmac_long_msg 3.890s 496.207us 1 1 100.00
hmac_back_pressure 7.170s 154.687us 1 1 100.00
hmac_datapath_stress 22.023m 8.465ms 1 1 100.00
hmac_burst_wr 5.190s 528.904us 1 1 100.00
hmac_stress_all 5.670s 606.683us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.470s 650.738us 1 1 100.00
hmac_long_msg 3.890s 496.207us 1 1 100.00
hmac_back_pressure 7.170s 154.687us 1 1 100.00
hmac_datapath_stress 22.023m 8.465ms 1 1 100.00
hmac_wipe_secret 1.008m 20.656ms 1 1 100.00
hmac_test_sha256_vectors 8.070s 729.740us 1 1 100.00
hmac_test_sha384_vectors 6.303m 11.213ms 1 1 100.00
hmac_test_sha512_vectors 18.710s 823.669us 1 1 100.00
hmac_test_hmac256_vectors 6.180s 202.477us 1 1 100.00
hmac_test_hmac384_vectors 6.390s 204.997us 1 1 100.00
hmac_test_hmac512_vectors 10.380s 345.697us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.470s 650.738us 1 1 100.00
hmac_long_msg 3.890s 496.207us 1 1 100.00
hmac_back_pressure 7.170s 154.687us 1 1 100.00
hmac_datapath_stress 22.023m 8.465ms 1 1 100.00
hmac_burst_wr 5.190s 528.904us 1 1 100.00
hmac_error 3.370s 329.648us 1 1 100.00
hmac_wipe_secret 1.008m 20.656ms 1 1 100.00
hmac_test_sha256_vectors 8.070s 729.740us 1 1 100.00
hmac_test_sha384_vectors 6.303m 11.213ms 1 1 100.00
hmac_test_sha512_vectors 18.710s 823.669us 1 1 100.00
hmac_test_hmac256_vectors 6.180s 202.477us 1 1 100.00
hmac_test_hmac384_vectors 6.390s 204.997us 1 1 100.00
hmac_test_hmac512_vectors 10.380s 345.697us 1 1 100.00
hmac_stress_all 5.670s 606.683us 1 1 100.00
V2 stress_all hmac_stress_all 5.670s 606.683us 1 1 100.00
V2 alert_test hmac_alert_test 0.610s 29.492us 1 1 100.00
V2 intr_test hmac_intr_test 0.590s 49.531us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.960s 1.607ms 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.960s 1.607ms 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.890s 164.227us 1 1 100.00
hmac_csr_rw 0.640s 37.290us 1 1 100.00
hmac_csr_aliasing 4.090s 397.828us 1 1 100.00
hmac_same_csr_outstanding 0.980s 206.275us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.890s 164.227us 1 1 100.00
hmac_csr_rw 0.640s 37.290us 1 1 100.00
hmac_csr_aliasing 4.090s 397.828us 1 1 100.00
hmac_same_csr_outstanding 0.980s 206.275us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.920s 303.642us 1 1 100.00
hmac_tl_intg_err 2.290s 695.937us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.290s 695.937us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.470s 650.738us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.970s 414.663us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 9.619m 138.337ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.280s 808.749us 1 1 100.00
TOTAL 28 28 100.00