I2C Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.360s	3.493ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.710s	2.822ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.850s	18.473us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.830s	62.840us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.770s	522.155us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.030s	135.769us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.840s	41.738us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.830s	62.840us	1	1	100.00
		i2c_csr_aliasing	1.030s	135.769us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.540s	64.561us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	13.079m	31.642ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	43.420s	4.876ms	1	1	100.00
V2	host_override	i2c_host_override	0.960s	15.852us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.380m	7.299ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.090s	5.834ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.190s	138.455us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.580s	715.100us	1	1	100.00
		i2c_host_fifo_reset_rx	3.870s	137.895us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.811m	2.615ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	5.620s	839.212us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.460s	132.643us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.300s	1.166ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	42.130s	29.150ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	6.440s	7.842ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.960s	769.657us	1	1	100.00
		i2c_target_intr_smoke	2.990s	543.842us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.920s	1.261ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.900s	433.964us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.965m	58.971ms	1	1	100.00
		i2c_target_stress_rd	11.960s	769.657us	1	1	100.00
		i2c_target_intr_stress_wr	30.480s	10.854ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.500s	1.431ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	50.810s	3.047ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.800s	950.788us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.730s	310.448us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.010s	1.121ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.030s	1.747ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	43.420s	4.876ms	1	1	100.00
		i2c_host_perf_precise	15.000s	2.874ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	5.620s	839.212us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.350s	156.862us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.410s	2.288ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.430s	456.708us	1	1	100.00
		i2c_target_nack_txstretch	1.740s	1.200ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	9.680s	337.752us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.780s	470.650us	1	1	100.00
V2	alert_test	i2c_alert_test	0.790s	19.491us	1	1	100.00
V2	intr_test	i2c_intr_test	0.830s	55.925us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.880s	1.118ms	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.880s	1.118ms	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.850s	18.473us	1	1	100.00
		i2c_csr_rw	0.830s	62.840us	1	1	100.00
		i2c_csr_aliasing	1.030s	135.769us	1	1	100.00
		i2c_same_csr_outstanding	0.850s	56.870us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.850s	18.473us	1	1	100.00
		i2c_csr_rw	0.830s	62.840us	1	1	100.00
		i2c_csr_aliasing	1.030s	135.769us	1	1	100.00
		i2c_same_csr_outstanding	0.850s	56.870us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	1.370s	324.881us	1	1	100.00
		i2c_sec_cm	1.160s	232.234us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.370s	324.881us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	22.310s	4.672ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.990s	21.038us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	5.540s	3.485ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.42753641578581083925200268527632360887749456627382846316479117647268848220830
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4672001847 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4672001847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.39595159545306934689103177690802993503287195696803831632886167297047388303552
      Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3484777580 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3484777580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.66990575730431473518102726590846900955344838266295465970912774639775356666450
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  64561366 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  64561366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.24001073487581241990238846917210274623316368595108894039563113645086186572614
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1165982861 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1165982861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.95579623664480977691164446052664404306279658195010896088474045378870619866182
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  21037690 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 221 [0xdd])
        UVM_INFO @  21037690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---