| V1 |
smoke |
keymgr_dpe_smoke |
3.372m |
63.700ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.960s |
24.411us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.920s |
61.347us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
4.070s |
450.071us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.030s |
88.432us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.440s |
110.696us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.920s |
61.347us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.030s |
88.432us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.720s |
21.568us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.690s |
10.617us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.250s |
180.214us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.250s |
180.214us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.960s |
24.411us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.920s |
61.347us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.030s |
88.432us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.140s |
94.244us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.960s |
24.411us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.920s |
61.347us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.030s |
88.432us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.140s |
94.244us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
8.060s |
1.499ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.740s |
587.527us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.510s |
308.286us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.510s |
308.286us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.510s |
308.286us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.510s |
308.286us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
2.200s |
1.034ms |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
8.060s |
1.499ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
8.060s |
1.499ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |