ROM_CTRL/64KB Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.550s 891.959us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 12.560s 210.024us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.030s 1.028ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.550s 1.584ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.700s 213.211us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.910s 4.248ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.030s 1.028ms 1 1 100.00
rom_ctrl_csr_aliasing 7.700s 213.211us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.970s 373.054us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.980s 577.367us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.150s 989.291us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.940s 3.518ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.850s 1.548ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 10.640s 292.056us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.120s 954.538us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.120s 954.538us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 12.560s 210.024us 1 1 100.00
rom_ctrl_csr_rw 7.030s 1.028ms 1 1 100.00
rom_ctrl_csr_aliasing 7.700s 213.211us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.280s 358.791us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 12.560s 210.024us 1 1 100.00
rom_ctrl_csr_rw 7.030s 1.028ms 1 1 100.00
rom_ctrl_csr_aliasing 7.700s 213.211us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.280s 358.791us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 43.090s 1.559ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.865m 752.769us 1 1 100.00
rom_ctrl_tl_intg_err 1.533m 773.240us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.865m 752.769us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.865m 752.769us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.865m 752.769us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.865m 752.769us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.550s 891.959us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.550s 891.959us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.550s 891.959us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.533m 773.240us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.850s 1.548ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.953m 14.715ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 43.090s 1.559ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.865m 752.769us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 54.580s 4.133ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00