SPI_DEVICE/1R1W Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.138m	255.869ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.940s	43.395us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.640s	581.847us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.650s	1.277ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.970s	337.951us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.380s	238.673us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.640s	581.847us	1	1	100.00
		spi_device_csr_aliasing	5.970s	337.951us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.870s	34.227us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.810s	232.574us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.970s	48.454us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.830s	1.545us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	3.493us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.950s	380.292us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.950s	380.292us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.270s	321.772us	1	1	100.00
		spi_device_tpm_sts_read	0.910s	130.426us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.810s	8.514ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.990s	4.629ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.080s	530.387us	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.080s	530.387us	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.930s	1.666ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.930s	1.666ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.930s	1.666ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.930s	1.666ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.930s	1.666ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.580s	4.565ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.306m	13.722ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.306m	13.722ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.306m	13.722ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.220s	337.293us	1	1	100.00
		spi_device_read_buffer_direct	4.490s	178.163us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.306m	13.722ms	1	1	100.00
		spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	53.130s	3.382ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.580s	710.606us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.580s	710.606us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.138m	255.869ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.497m	9.013ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.178m	30.726ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.900s	25.527us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.890s	52.617us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.290s	142.784us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.290s	142.784us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.940s	43.395us	1	1	100.00
		spi_device_csr_rw	1.640s	581.847us	1	1	100.00
		spi_device_csr_aliasing	5.970s	337.951us	1	1	100.00
		spi_device_same_csr_outstanding	1.670s	114.908us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.940s	43.395us	1	1	100.00
		spi_device_csr_rw	1.640s	581.847us	1	1	100.00
		spi_device_csr_aliasing	5.970s	337.951us	1	1	100.00
		spi_device_same_csr_outstanding	1.670s	114.908us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.430s	61.583us	1	1	100.00
		spi_device_tl_intg_err	5.760s	1.335ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.760s	1.335ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	23.190s	86.006ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.5642651735593489810799468941699144919976544262886929218377554328742209585035
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    950959 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[29])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    950959 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    950959 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.54120184934869926669859776518541505346652796474484210563458181591226717076553
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    761393 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x18bd7b [110001011110101111011] vs 0x0 [0])
        UVM_ERROR @    855393 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdeb993 [110111101011100110010011] vs 0x0 [0])
        UVM_ERROR @    894393 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa13f28 [101000010011111100101000] vs 0x0 [0])
        UVM_ERROR @    954393 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xed5867 [111011010101100001100111] vs 0x0 [0])
        UVM_ERROR @    983393 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12eae3 [100101110101011100011] vs 0x0 [0])