SPI_HOST Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	2.929ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	16.430us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	24.820us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	2.067ms	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	59.855us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	40.675us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	24.820us	1	1	100.00
		spi_host_csr_aliasing	1.000s	59.855us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	25.315us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	30.343us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	10.000s	40.550us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	10.000s	230.518us	1	1	100.00
		spi_host_error_cmd	9.000s	17.093us	1	1	100.00
		spi_host_event	20.000s	1.191ms	1	1	100.00
V2	clock_rate	spi_host_speed	12.000s	457.054us	1	1	100.00
V2	speed	spi_host_speed	12.000s	457.054us	1	1	100.00
V2	chip_select_timing	spi_host_speed	12.000s	457.054us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	21.000s	635.415us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	9.000s	30.252us	1	1	100.00
V2	cpol_cpha	spi_host_speed	12.000s	457.054us	1	1	100.00
V2	full_cycle	spi_host_speed	12.000s	457.054us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	2.929ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	2.929ms	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	42.221us	1	1	100.00
V2	spien	spi_host_spien	9.000s	232.229us	1	1	100.00
V2	stall	spi_host_status_stall	8.033m	15.994ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	10.000s	343.001us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	10.000s	230.518us	1	1	100.00
V2	alert_test	spi_host_alert_test	6.000s	21.086us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	16.066us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	229.106us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	229.106us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	16.430us	1	1	100.00
		spi_host_csr_rw	2.000s	24.820us	1	1	100.00
		spi_host_csr_aliasing	1.000s	59.855us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	16.793us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	16.430us	1	1	100.00
		spi_host_csr_rw	2.000s	24.820us	1	1	100.00
		spi_host_csr_aliasing	1.000s	59.855us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	16.793us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	59.718us	1	1	100.00
		spi_host_sec_cm	7.000s	44.403us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	59.718us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.283m	1.968ms	1	1	100.00
		TOTAL			26	26	100.00