SRAM_CTRL/RET Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.390s	495.727us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.750s	34.962us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	14.331us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.200s	55.383us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.680s	17.084us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.970s	24.986us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	14.331us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	17.084us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.360s	482.070us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.560s	236.988us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.522m	13.268ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.201m	5.223ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.880s	4.080ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.750s	2.914ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.120s	1.183ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.795m	2.079ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.470s	74.100us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.035m	26.311ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	50.530s	614.764us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.720s	106.043us	1	1	100.00
		sram_ctrl_throughput_w_readback	53.670s	281.404us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.772m	10.483ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.800s	89.778us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	25.054m	32.199ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.690s	12.736us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.930s	65.699us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.930s	65.699us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.750s	34.962us	1	1	100.00
		sram_ctrl_csr_rw	0.700s	14.331us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	17.084us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.334us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.750s	34.962us	1	1	100.00
		sram_ctrl_csr_rw	0.700s	14.331us	1	1	100.00
		sram_ctrl_csr_aliasing	0.680s	17.084us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	27.334us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.460s	431.793us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.840s	6.624us	0	1	0.00
		sram_ctrl_tl_intg_err	1.160s	322.218us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.840s	6.624us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.160s	322.218us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.772m	10.483ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.772m	10.483ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	14.331us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.795m	2.079ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.795m	2.079ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.795m	2.079ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.120s	1.183ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.210s	153.354us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.460s	431.793us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.370s	45.790us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.390s	495.727us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.390s	495.727us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.795m	2.079ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.840s	6.624us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.120s	1.183ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.840s	6.624us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.840s	6.624us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.390s	495.727us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.840s	6.624us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.340m	1.392ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.18785668640627587579316018144976839370577407047815502288149612769014712005883
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6624182 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6624182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---