UART Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: 9baed2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.180s	532.089us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	35.294us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.600s	25.846us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.780s	357.831us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.720s	117.722us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.610s	122.095us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.600s	25.846us	1	1	100.00
		uart_csr_aliasing	0.720s	117.722us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	8.600s	28.219ms	1	1	100.00
V2	parity	uart_smoke	1.180s	532.089us	1	1	100.00
		uart_tx_rx	8.600s	28.219ms	1	1	100.00
V2	parity_error	uart_intr	18.740s	14.482ms	1	1	100.00
		uart_rx_parity_err	8.780s	114.819ms	1	1	100.00
V2	watermark	uart_tx_rx	8.600s	28.219ms	1	1	100.00
		uart_intr	18.740s	14.482ms	1	1	100.00
V2	fifo_full	uart_fifo_full	46.720s	57.860ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.119m	63.219ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	17.530s	77.150ms	1	1	100.00
V2	rx_frame_err	uart_intr	18.740s	14.482ms	1	1	100.00
V2	rx_break_err	uart_intr	18.740s	14.482ms	1	1	100.00
V2	rx_timeout	uart_intr	18.740s	14.482ms	1	1	100.00
V2	perf	uart_perf	1.771m	12.082ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.850s	2.190ms	1	1	100.00
V2	line_loopback	uart_loopback	2.850s	2.190ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	20.200s	57.162ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.770s	2.512ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.060s	1.880ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	1.810s	1.272ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.635m	141.312ms	1	1	100.00
V2	stress_all	uart_stress_all	1.401m	278.577ms	1	1	100.00
V2	alert_test	uart_alert_test	0.580s	23.180us	1	1	100.00
V2	intr_test	uart_intr_test	0.710s	17.457us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.110s	197.879us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.110s	197.879us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	35.294us	1	1	100.00
		uart_csr_rw	0.600s	25.846us	1	1	100.00
		uart_csr_aliasing	0.720s	117.722us	1	1	100.00
		uart_same_csr_outstanding	0.710s	35.042us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	35.294us	1	1	100.00
		uart_csr_rw	0.600s	25.846us	1	1	100.00
		uart_csr_aliasing	0.720s	117.722us	1	1	100.00
		uart_same_csr_outstanding	0.710s	35.042us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.810s	265.769us	1	1	100.00
		uart_tl_intg_err	0.830s	293.190us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.830s	293.190us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	17.520s	10.013ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.111284976376980583488388367361289047295187758572380474186505752031115671789379
      Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 55428089722 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 55428128184 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 55428166646 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (253 [0xfd] vs 191 [0xbf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 55714208540 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7,                                 clk_pulses: 0
        UVM_ERROR @ 55714247002 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty