CHIP Simulation Results

Wednesday November 05 2025 16:07:17 UTC

GitHub Revision: `9baed2b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.776m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.776m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.296m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.356m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.001m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.426m	275.582us	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.426m	275.582us	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.426m	275.582us	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	29.140s	10.300us	0	1	0.00
		chip_sw_example_manufacturer	2.317m		0	1	0.00
		chip_sw_example_concurrency	3.449m	150.353us	1	1	100.00
		chip_sw_uart_smoketest_signed	9.662s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.480s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.950s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.950s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.320s	11.621us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.683m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	45.693m	4.328ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.228m	282.152us	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	23.531s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.112s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	45.962s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	48.749s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.060s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.060s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.790m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.767m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.808m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.808m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.007m	117.032us	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	1.973m	117.013us	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.395m	272.147us	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.727s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.199s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.589m	512.256us	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.806m	248.756us	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	10.394m	606.570us	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	10.394m	606.570us	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.416s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	3.789m	164.308us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	3.789m	164.308us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.922m	2.272ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.899m	146.394us	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.754m	225.703us	1	1	100.00
		chip_sw_aes_idle	3.383m	147.259us	1	1	100.00
		chip_sw_hmac_enc_idle	3.520m	161.619us	1	1	100.00
		chip_sw_kmac_idle	2.891m	145.026us	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.336m	165.664us	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	3.274m	165.648us	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	3.331m	165.664us	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	3.478m	165.664us	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.953s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	9.852s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	9.257s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.348s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.940s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.510s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.005s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.953s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	9.852s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	9.257s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.348s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.940s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.510s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.005s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	39.890s	10.400us	0	1	0.00
		chip_sw_aes_enc_jitter_en	38.020s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.850s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.120s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.910s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.071s		0	1	0.00
		chip_sw_clkmgr_jitter	3.071m	141.859us	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	6.203m	1.779ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	44.610s	10.160us	0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	39.060s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	41.040s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.160s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	40.540s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	38.540s	10.100us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.251s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.032s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.313s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.724s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	33.990s	10.380us	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.722m	500.490us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	3.789m	164.308us	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.389s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.722m	500.490us	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.933s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15.423s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	16.951s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	36.575s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.070s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	33.990s	10.380us	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.395m	272.147us	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	6.855m	375.216us	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.861m	267.388us	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	6.856m	318.068us	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.937m	144.166us	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	33.990s	10.380us	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.410s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.526s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	33.990s	10.380us	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.038s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	6.856m	318.068us	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.415s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.150s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.623s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.777s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.395s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.347s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.526s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.495s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.310m	268.308us	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.443s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.907s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	38.596s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	32.454s		0	1	0.00
		chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	4.766m	268.247us	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	13.909m	1.267ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.753s		0	1	0.00
		chip_prim_tl_access	5.175m	386.070us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.953s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	9.852s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	9.257s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	9.348s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	9.940s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.510s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.005s		0	1	0.00
		chip_rv_dm_lc_disabled	6.589m	512.256us	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.375m	157.123us	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.020s	10.220us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.047m	145.833us	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.383m	147.259us	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.693m	156.384us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	37.850s	10.280us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.520m	161.619us	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.129m	148.965us	1	1	100.00
		chip_sw_kmac_mode_kmac	3.832m	172.146us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	35.910s	10.280us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	4.766m	268.247us	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	33.870s	10.160us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.952m	209.501us	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.891m	145.026us	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	7.468m	286.053us	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	7.468m	286.053us	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.225s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.359m	156.787us	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	9.266s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	4.766m	268.247us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.120s	10.380us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	39.716m	1.472ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	39.890s	10.400us	0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.754m	225.703us	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.754m	225.703us	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.754m	225.703us	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.223m	264.371us	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.909m	1.267ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.909m	1.267ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.436m	322.256us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.071s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.753s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	33.990s	10.380us	0	1	0.00
		chip_sw_data_integrity_escalation	1.808m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.223m	264.371us	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	4.766m	268.247us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	6.436m	322.256us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.036m	160.412us	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.223m	264.371us	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	4.766m	268.247us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	6.436m	322.256us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.036m	160.412us	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	9.928s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.495s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.443s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.907s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	38.596s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	32.454s		0	1	0.00
		chip_sw_lc_ctrl_transition	33.394s		0	1	0.00
		chip_prim_tl_access	5.175m	386.070us	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.175m	386.070us	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	10.022s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	28.878s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.032s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	39.890s	10.400us	0	1	0.00
		chip_sw_aes_enc_jitter_en	38.020s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	37.850s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.120s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.910s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.071s		0	1	0.00
		chip_sw_clkmgr_jitter	3.071m	141.859us	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	2.895m	143.568us	0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	2.895m	143.568us	0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.763m	155.076us	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.127m	138.775us	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.032m	159.464us	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.342m	251.554us	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.846m	160.221us	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.315m	164.732us	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.036m	160.412us	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	6.855m	375.216us	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	6.855m	375.216us	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	2.532m	157.104us	1	1	100.00
		chip_sw_aon_timer_smoketest	2.694m	163.223us	1	1	100.00
		chip_sw_clkmgr_smoketest	2.412m	142.922us	1	1	100.00
		chip_sw_csrng_smoketest	2.350m	144.792us	1	1	100.00
		chip_sw_gpio_smoketest	2.585m	165.754us	1	1	100.00
		chip_sw_hmac_smoketest	3.066m	182.015us	1	1	100.00
		chip_sw_kmac_smoketest	3.018m	171.073us	1	1	100.00
		chip_sw_otbn_smoketest	3.558m	208.414us	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.394m	148.040us	1	1	100.00
		chip_sw_rv_plic_smoketest	2.309m	145.048us	1	1	100.00
		chip_sw_rv_timer_smoketest	3.428m	248.775us	1	1	100.00
		chip_sw_rstmgr_smoketest	2.330m	141.617us	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.416m	145.507us	1	1	100.00
		chip_sw_uart_smoketest	2.546m	157.719us	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.497s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	9.662s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.683m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.365s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.576m	192.124us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.723m	216.919us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.057m	218.624us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.503m	228.605us	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	33.138s		0	1	0.00
		chip_rv_dm_lc_disabled	6.589m	512.256us	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	18.296s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.676s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	16.371s		0	1	0.00
		chip_sw_lc_walkthrough_rma	10.616s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	33.138s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.083m	705.073us	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.342m	722.833us	1	1	100.00
		rom_volatile_raw_unlock	9.323s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	9.368s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.603m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.730m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.018m	118.103us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.018m	118.103us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.950s		0	1	0.00
		chip_same_csr_outstanding	8.610s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.950s		0	1	0.00
		chip_same_csr_outstanding	8.610s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.437m	436.039us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.360s	11.258us	1	1	100.00
		xbar_smoke_large_delays	4.300m	2.090ms	1	1	100.00
		xbar_smoke_slow_rsp	4.963m	1.693ms	1	1	100.00
		xbar_random_zero_delays	58.200s	52.316us	1	1	100.00
		xbar_random_large_delays	16.071m	7.641ms	1	1	100.00
		xbar_random_slow_rsp	24.241m	8.207ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.763m	202.206us	1	1	100.00
		xbar_error_and_unmapped_addr	1.752m	226.180us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	44.050s	43.747us	1	1	100.00
		xbar_error_and_unmapped_addr	1.752m	226.180us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.352m	460.880us	1	1	100.00
		xbar_access_same_device_slow_rsp	43.808m	16.119ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	38.080s	34.201us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.452m	445.060us	1	1	100.00
		xbar_stress_all_with_error	2.788m	152.783us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.923m	199.115us	1	1	100.00
		xbar_stress_all_with_reset_error	14.035m	534.717us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.226s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	9.747s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.057s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.076s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.179s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	9.947s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.023s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	9.628s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.372s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.831s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.373s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.297s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	9.838s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.094m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.262m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.223m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.127m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	49.294s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.041m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.173m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.016m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.261m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	58.929s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	55.050s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	54.158s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	52.741s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	36.988s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	42.614s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	14.481s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.979s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	9.644s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	10.135s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	10.490s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	10.868s		0	1	0.00
		rom_e2e_asm_init_dev	9.471s		0	1	0.00
		rom_e2e_asm_init_prod	10.426s		0	1	0.00
		rom_e2e_asm_init_prod_end	9.609s		0	1	0.00
		rom_e2e_asm_init_rma	10.525s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	9.893s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	9.941s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.034s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.876s		0	1	0.00
V2		TOTAL			68	205	33.17
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.587m	165.737us	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.646m	131.584us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	9.863s		0	1	0.00
		rom_e2e_jtag_debug_dev	9.691s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.628s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.715s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	33.990s	10.380us	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	56.751s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.484m	158.752us	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	10.218s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.096s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	9.863s		0	1	0.00
		rom_e2e_jtag_debug_dev	9.691s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.628s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	9.608s		0	1	0.00
		rom_e2e_jtag_inject_dev	14.065s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.526s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.439s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	16.765m	921.868us	1	1	100.00
		chip_sw_entropy_src_kat_test	3.006m	144.288us	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.796m	141.560us	1	1	100.00
		chip_plic_all_irqs_0	7.480m	351.569us	1	1	100.00
		chip_plic_all_irqs_10	8.316m	382.656us	1	1	100.00
		chip_sw_dma_inline_hashing	3.234m	191.525us	1	1	100.00
		chip_sw_dma_abort	3.345m	179.988us	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	9.632s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.472s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	9.414s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.058s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	9.587s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	9.850s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	9.612s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	9.918s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	9.356s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	9.351s		0	1	0.00
		chip_sw_entropy_src_smoketest	2.900m	170.752us	1	1	100.00
		chip_sw_mbx_smoketest	6.065m	427.662us	1	1	100.00
		TOTAL			81	250	32.40

Failure Buckets

Job returned non-zero exit code has 130 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.20385320500644268093805689455730303952249649596684062789610683138270013819638
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.716s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.23525638213555178108372182526005889290562224241350161633827708525132786693485
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 99.705s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.39047751870742269780296099412353402868711335132386479744857992406649299650233
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 98.688s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.113191134360453651756283775900768958482149059314235452846145361432482023869619
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 97.277s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.58651856704421469828791790048207383890881891484856536776938057539612154482658
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 97.710s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 125 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 11 failures:
- Test chip_sw_otbn_ecdsa_op_irq_jitter_en has 1 failures.
  - 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.111101382279585947367172803958878707641412465583051586315039657020232826413481
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.18238461668673118472100835493192455164775887564420523241675460772188395514013
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.92132623360048391727501078923746920799261228023789069901141947270590035561515
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.26907062316422141668965566034160792489263630023469577169634420927271854862851
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.45744708310529055379719775307314969474360574775054452272939215945505617210309
    Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 6 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.109511667051280524931417103875991483915169882010531735104394140050937109374601
    Line 452, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 375.216000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 375.216000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_soc_proxy_smoketest has 1 failures.
  - 0.chip_sw_soc_proxy_smoketest.65456312009601654401140038385721439390575617272066170747272433720703697589055
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
```
      Offending '((!rstreqs[1]) && (reset_cause != HwReq))'
  UVM_ERROR @ 143.568000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 143.568000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.58978415822712300003278717940369769279976353776413526520691037714538986910790
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.10701590950388411970697128115459175341888973010688647178021140269960829130888
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.648000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.21808227207757313360464752608062492337868008880675453854461841140877723204718
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
      Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
  UVM_ERROR @ 165.664000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
  UVM_INFO @ 165.664000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.58640605364227177548375025200831905159979884828187522733749566712217479777382
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.28205623794431440040626988758509532989950718271840143072240257865494299218889
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.112022214444844162219366897813168175955276954874043233236164161077101899044174
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.103458711025866408458297205883930797505107066371036026452740554800761613315856
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 268.247000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12846346242971680294842162095278290008764511965792100781143972124597745804378381624522470519821269378646930143133668436094702747161983540854563732065705052 [0xf547a1e7aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3731111167f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.247000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.93309862929016354654556256031525672102542458319537178267087037884047555686552
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 268.308000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11090392789561953912119093097643318087076778150023542369767475220518192828377299306546280739518747945794748842293697297497628693691888937552425483636137052 [0xd3c0b5f3aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3559605027f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 268.308000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.64855250833323876662397246332896798476183808375218153076811062535800744563847
Line 6256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 117.032000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: 'h30480000  a_data: 'h20092ca5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h0  a_user: 'h2696d  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.032000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.38801052575747233423634624748908552096538239950139921955621591455636134936042
Line 6256, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 117.013000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47263) { a_addr: 'h30480000  a_data: 'h332195b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h1  a_user: 'h24886  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 117.013000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.99874324260972611545074588412743185846825586208500139177287355799280137009073
    Line 566, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.79507125859404132812094862787474827835875576078915762148042318308712251828244
    Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.380001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.43522079116600377569733619023302416739588745324748879367235430838885497313120
    Line 466, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 282.152000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 282.152000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.19037950600766242268840073233056259100998150538446247736175048360648748666017
    Line 471, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 158.752000 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 158.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.91146582522151796409842554554729521088823371124602449548924657427000908877289
    Line 670, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 318.068000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 318.068000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.50580253210438766006394688541192994573095504934449831681124100139158436587270
    Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 155.076000 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 155.076000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.92128645078748342004208960686533288329065908470584647625396652198667090233663
    Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 138.775000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 138.775000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.78435973849806779570295337588495502973882920142093413096736395416387222593227
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 606.570000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4678 usec which is not in the range 427 usec and 486 usec
  UVM_INFO @ 606.570000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.14262144847559130594216223192988020374611222230135967995013220613780383029804
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 164.308000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 164.308000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.79420888380172894122430258600700154619949625018075699462182847533612629940047
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 251.554000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 251.554000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.41065542838077354418999372568120091168888905880193212050498735852603366718573
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.33267373408737404436602300995350957598713491298609811339300094534076673288954
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 118.103000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 118.103000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.76272609797343698591735886095167112628122401528089841334212788335460811141697
    Line 240, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 512.256000 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40794 read out mismatch
  UVM_INFO @ 512.256000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.40082760913453713573811426812603746348255241211085639576548743579228802327587
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.107623076355445665682595891139422545884360936131426383737335625718415675734572
    Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_ERROR @ 179.988000 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 179.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```