AES/MASKED Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	95.629us	1	1	100.00
V1	smoke	aes_smoke	3.000s	240.925us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	91.635us	1	1	100.00
V1	csr_rw	aes_csr_rw	3.000s	76.699us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	184.313us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	109.320us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	66.100us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	76.699us	1	1	100.00
		aes_csr_aliasing	3.000s	109.320us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	240.925us	1	1	100.00
		aes_config_error	3.000s	155.049us	1	1	100.00
		aes_stress	7.000s	145.708us	1	1	100.00
V2	key_length	aes_smoke	3.000s	240.925us	1	1	100.00
		aes_config_error	3.000s	155.049us	1	1	100.00
		aes_stress	7.000s	145.708us	1	1	100.00
V2	back2back	aes_stress	7.000s	145.708us	1	1	100.00
		aes_b2b	7.000s	364.692us	1	1	100.00
V2	backpressure	aes_stress	7.000s	145.708us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	240.925us	1	1	100.00
		aes_config_error	3.000s	155.049us	1	1	100.00
		aes_stress	7.000s	145.708us	1	1	100.00
		aes_alert_reset	3.000s	94.132us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	110.974us	1	1	100.00
		aes_config_error	3.000s	155.049us	1	1	100.00
		aes_alert_reset	3.000s	94.132us	1	1	100.00
V2	trigger_clear_test	aes_clear	2.000s	164.872us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	339.707us	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	94.132us	1	1	100.00
V2	stress	aes_stress	7.000s	145.708us	1	1	100.00
V2	sideload	aes_stress	7.000s	145.708us	1	1	100.00
		aes_sideload	5.000s	199.441us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	154.264us	1	1	100.00
V2	stress_all	aes_stress_all	4.000s	302.647us	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	59.904us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	275.295us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	275.295us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	91.635us	1	1	100.00
		aes_csr_rw	3.000s	76.699us	1	1	100.00
		aes_csr_aliasing	3.000s	109.320us	1	1	100.00
		aes_same_csr_outstanding	3.000s	274.620us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	91.635us	1	1	100.00
		aes_csr_rw	3.000s	76.699us	1	1	100.00
		aes_csr_aliasing	3.000s	109.320us	1	1	100.00
		aes_same_csr_outstanding	3.000s	274.620us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	65.323us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	137.561us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	137.561us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	137.561us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	137.561us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	95.687us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	546.322us	1	1	100.00
		aes_tl_intg_err	3.000s	185.366us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	185.366us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	94.132us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	137.561us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	240.925us	1	1	100.00
		aes_stress	7.000s	145.708us	1	1	100.00
		aes_alert_reset	3.000s	94.132us	1	1	100.00
		aes_core_fi	3.000s	155.533us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	137.561us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	57.071us	1	1	100.00
		aes_stress	7.000s	145.708us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	145.708us	1	1	100.00
		aes_sideload	5.000s	199.441us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	57.071us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	57.071us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	57.071us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	57.071us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	57.071us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	145.708us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	145.708us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	360.264us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
		aes_ctr_fi	3.000s	84.091us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	360.264us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	180.948us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	360.264us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	3.000s	84.091us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
		aes_ctr_fi	3.000s	84.091us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	94.132us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
		aes_ctr_fi	3.000s	84.091us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
		aes_ctr_fi	3.000s	84.091us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	3.000s	84.091us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	360.264us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	180.948us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	31.000s	3.095ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.105570948928718123839801509859268296279241670345834302911119540450099177899255
      Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.88983331172834865064514926335729215889450267959018161173708216517237707973021
      Line 1127, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3094517568 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 3094517568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---