DMA Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	191.637us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	234.730us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	297.819us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	477.554us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	36.341us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	3.805ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	5.000s	2.867ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	84.185us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	36.341us	1	1	100.00
		dma_csr_aliasing	5.000s	2.867ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.417m	13.598ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	20.783m	245.056ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	4.417m	22.495ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.417m	22.495ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	20.783m	245.056ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	12.833m	76.902ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.417m	22.495ms	1	1	100.00
V2	dma_abort	dma_abort	4.000s	449.204us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.683m	7.542ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	15.582us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	83.816us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	614.188us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	614.188us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	477.554us	1	1	100.00
		dma_csr_rw	2.000s	36.341us	1	1	100.00
		dma_csr_aliasing	5.000s	2.867ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	37.096us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	477.554us	1	1	100.00
		dma_csr_rw	2.000s	36.341us	1	1	100.00
		dma_csr_aliasing	5.000s	2.867ms	1	1	100.00
		dma_same_csr_outstanding	2.000s	37.096us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	13.000s	235.879us	1	1	100.00
		dma_generic_stress	12.833m	76.902ms	1	1	100.00
		dma_handshake_stress	4.417m	22.495ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	334.049us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	152.689us	1	1	100.00
		dma_sec_cm	2.000s	13.830us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	2.133m	14.701ms	1	1	100.00
		dma_longer_transfer	3.000s	80.817us	1	1	100.00
		dma_stress_all_with_rand_reset	16.000s	983.329us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.69083377428667858003386652106914171058711408338344588607481044337258000248678
      Line 128, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  983328911ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  983328911ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---