HMAC Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.250s		1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s		1	1	100.00
V1	csr_rw	hmac_csr_rw	0.780s		1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.400s		1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	4.490s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.599m		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.780s		1	1	100.00
		hmac_csr_aliasing	4.490s		1	1	100.00
V1		TOTAL			6	6	100.00
V2	long_msg	hmac_long_msg	42.280s		1	1	100.00
V2	back_pressure	hmac_back_pressure	46.740s		1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	8.540s		1	1	100.00
		hmac_test_sha384_vectors	20.060s		1	1	100.00
		hmac_test_sha512_vectors	20.390s		1	1	100.00
		hmac_test_hmac256_vectors	9.620s		1	1	100.00
		hmac_test_hmac384_vectors	7.440s		1	1	100.00
		hmac_test_hmac512_vectors	9.990s		1	1	100.00
V2	burst_wr	hmac_burst_wr	3.930s		1	1	100.00
V2	datapath_stress	hmac_datapath_stress	2.677m		1	1	100.00
V2	error	hmac_error	5.070s		1	1	100.00
V2	wipe_secret	hmac_wipe_secret	0.770s		1	1	100.00
V2	save_and_restore	hmac_smoke	4.250s		1	1	100.00
		hmac_long_msg	42.280s		1	1	100.00
		hmac_back_pressure	46.740s		1	1	100.00
		hmac_datapath_stress	2.677m		1	1	100.00
		hmac_burst_wr	3.930s		1	1	100.00
		hmac_stress_all	22.290m		1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	4.250s		1	1	100.00
		hmac_long_msg	42.280s		1	1	100.00
		hmac_back_pressure	46.740s		1	1	100.00
		hmac_datapath_stress	2.677m		1	1	100.00
		hmac_wipe_secret	0.770s		1	1	100.00
		hmac_test_sha256_vectors	8.540s		1	1	100.00
		hmac_test_sha384_vectors	20.060s		1	1	100.00
		hmac_test_sha512_vectors	20.390s		1	1	100.00
		hmac_test_hmac256_vectors	9.620s		1	1	100.00
		hmac_test_hmac384_vectors	7.440s		1	1	100.00
		hmac_test_hmac512_vectors	9.990s		1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	4.250s		1	1	100.00
		hmac_long_msg	42.280s		1	1	100.00
		hmac_back_pressure	46.740s		1	1	100.00
		hmac_datapath_stress	2.677m		1	1	100.00
		hmac_burst_wr	3.930s		1	1	100.00
		hmac_error	5.070s		1	1	100.00
		hmac_wipe_secret	0.770s		1	1	100.00
		hmac_test_sha256_vectors	8.540s		1	1	100.00
		hmac_test_sha384_vectors	20.060s		1	1	100.00
		hmac_test_sha512_vectors	20.390s		1	1	100.00
		hmac_test_hmac256_vectors	9.620s		1	1	100.00
		hmac_test_hmac384_vectors	7.440s		1	1	100.00
		hmac_test_hmac512_vectors	9.990s		1	1	100.00
		hmac_stress_all	22.290m		1	1	100.00
V2	stress_all	hmac_stress_all	22.290m		1	1	100.00
V2	alert_test	hmac_alert_test	0.560s		1	1	100.00
V2	intr_test	hmac_intr_test	0.600s		1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.340s		1	1	100.00
V2	tl_d_illegal_access	hmac_tl_errors	1.340s		1	1	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s		1	1	100.00
		hmac_csr_rw	0.780s		1	1	100.00
		hmac_csr_aliasing	4.490s		1	1	100.00
		hmac_same_csr_outstanding	1.580s		1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s		1	1	100.00
		hmac_csr_rw	0.780s		1	1	100.00
		hmac_csr_aliasing	4.490s		1	1	100.00
		hmac_same_csr_outstanding	1.580s		1	1	100.00
V2		TOTAL			17	17	100.00
V2S	tl_intg_err	hmac_sec_cm	1.070s		1	1	100.00
		hmac_tl_intg_err	3.590s		1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.590s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.250s		1	1	100.00
V3	stress_reset	hmac_stress_reset	2.230s		1	1	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	32.300s		1	1	100.00
V3		TOTAL			2	2	100.00
	Unmapped tests	hmac_directed	1.880s		1	1	100.00
		TOTAL			28	28	100.00