I2C Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	29.780s		1	1	100.00
V1	target_smoke	i2c_target_smoke	27.220s		1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.730s		1	1	100.00
V1	csr_rw	i2c_csr_rw	0.740s		1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.950s		1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.650s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.910s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.740s		1	1	100.00
		i2c_csr_aliasing	1.650s		1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.180s		0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.157m		0	1	0.00
V2	host_maxperf	i2c_host_perf	36.750s		1	1	100.00
V2	host_override	i2c_host_override	0.650s		1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.762m		1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	57.890s		1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.870s		1	1	100.00
		i2c_host_fifo_fmt_empty	3.240s		1	1	100.00
		i2c_host_fifo_reset_rx	7.750s		1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.200m		1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.680s		1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.580s		1	1	100.00
V2	target_glitch	i2c_target_glitch	1.960s		0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.397m		1	1	100.00
V2	target_maxperf	i2c_target_perf	3.420s		1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.530s		1	1	100.00
		i2c_target_intr_smoke	4.120s		1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.980s		1	1	100.00
		i2c_target_fifo_reset_tx	1.000s		1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	51.600s		1	1	100.00
		i2c_target_stress_rd	12.530s		1	1	100.00
		i2c_target_intr_stress_wr	18.270s		1	1	100.00
V2	target_timeout	i2c_target_timeout	5.140s		1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	49.340s		1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.520s		1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.130s		1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.210s		1	1	100.00
		i2c_target_fifo_watermarks_tx	1.390s		1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	36.750s		1	1	100.00
		i2c_host_perf_precise	1.640s		1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.680s		1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.720s		1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.110s		1	1	100.00
		i2c_target_nack_acqfull_addr	2.000s		1	1	100.00
		i2c_target_nack_txstretch	1.130s		1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.650s		1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.760s		1	1	100.00
V2	alert_test	i2c_alert_test	0.620s		1	1	100.00
V2	intr_test	i2c_intr_test	0.810s		1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.300s		1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.300s		1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.730s		1	1	100.00
		i2c_csr_rw	0.740s		1	1	100.00
		i2c_csr_aliasing	1.650s		1	1	100.00
		i2c_same_csr_outstanding	1.020s		1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.730s		1	1	100.00
		i2c_csr_rw	0.740s		1	1	100.00
		i2c_csr_aliasing	1.650s		1	1	100.00
		i2c_same_csr_outstanding	1.020s		1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.290s		1	1	100.00
		i2c_sec_cm	0.840s		1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.290s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.970s		0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.040s		0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	32.260s		0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.70212278362339470284270844631125738636270367957955862576092926650075449970238
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  53985978 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  53985978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.23177153276106165193484436303555418109123318987093849591526358497959114372661
      Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 36744587263 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 36744587263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.101524808188507914621318640859234792333824994131970542849742674681470369434648
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2881352867 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2881352867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.70559302649839569072676966836226299951317157325336764806290160479174804599563
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 167364801 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 217 [0xd9])
        UVM_INFO @ 167364801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.110875325861289395851916407012999876547053458328372049154004737742524948017050
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1833400635 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1833400635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.44012550928374857839639047978172352108653954377966761899878476196347043882801
      Line 135, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1583266079 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1583266079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---