KMAC/UNMASKED Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.570s		1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.000s		1	1	100.00
V1	csr_rw	kmac_csr_rw	0.880s		1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.910s		1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.670s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.880s		1	1	100.00
		kmac_csr_aliasing	7.670s		1	1	100.00
V1	mem_walk	kmac_mem_walk	0.850s		1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.140s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.650s		1	1	100.00
V2	burst_write	kmac_burst_write	10.738m		1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	20.575m		1	1	100.00
		kmac_test_vectors_sha3_256	25.606m		1	1	100.00
		kmac_test_vectors_sha3_384	22.372m		1	1	100.00
		kmac_test_vectors_sha3_512	13.610s		1	1	100.00
		kmac_test_vectors_shake_128	2.210m		1	1	100.00
		kmac_test_vectors_shake_256	19.858m		1	1	100.00
		kmac_test_vectors_kmac	2.350s		1	1	100.00
		kmac_test_vectors_kmac_xof	2.010s		1	1	100.00
V2	sideload	kmac_sideload	23.260s		1	1	100.00
V2	app	kmac_app	50.050s		1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.220m		1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.341m		1	1	100.00
V2	error	kmac_error	3.723m		1	1	100.00
V2	key_error	kmac_key_error	4.290s		1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	15.520s		0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	5.310s		1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.850s		1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	14.630s		1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.620s		1	1	100.00
V2	stress_all	kmac_stress_all	1.610s		1	1	100.00
V2	intr_test	kmac_intr_test	0.940s		1	1	100.00
V2	alert_test	kmac_alert_test	1.060s		1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.770s		1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.770s		1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.000s		1	1	100.00
		kmac_csr_rw	0.880s		1	1	100.00
		kmac_csr_aliasing	7.670s		1	1	100.00
		kmac_same_csr_outstanding	1.300s		1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.000s		1	1	100.00
		kmac_csr_rw	0.880s		1	1	100.00
		kmac_csr_aliasing	7.670s		1	1	100.00
		kmac_same_csr_outstanding	1.300s		1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s		1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s		1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s		1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s		1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.160s		1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	24.550s		1	1	100.00
		kmac_tl_intg_err	3.700s		1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.700s		1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.620s		1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.570s		1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	23.260s		1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s		1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.550s		1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.550s		1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.550s		1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.570s		1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.620s		1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.550s		1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	52.430s		1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.570s		1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.677m		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.83659463517689182649759297876350274426845769966011382404276953834501154604246
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10464854153 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4fe2c000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10464854153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---