ROM_CTRL/32KB Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	3.870s		1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.630s		1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.210s		1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.040s		1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.400s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.900s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.210s		1	1	100.00
		rom_ctrl_csr_aliasing	4.400s		1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.550s		1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.190s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.810s		1	1	100.00
V2	stress_all	rom_ctrl_stress_all	18.580s		1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.980s		1	1	100.00
V2	alert_test	rom_ctrl_alert_test	5.120s		1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.290s		1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.290s		1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.630s		1	1	100.00
		rom_ctrl_csr_rw	4.210s		1	1	100.00
		rom_ctrl_csr_aliasing	4.400s		1	1	100.00
		rom_ctrl_same_csr_outstanding	5.570s		1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.630s		1	1	100.00
		rom_ctrl_csr_rw	4.210s		1	1	100.00
		rom_ctrl_csr_aliasing	4.400s		1	1	100.00
		rom_ctrl_same_csr_outstanding	5.570s		1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	18.150s		1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.721m		0	1	0.00
		rom_ctrl_tl_intg_err	26.590s		1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.721m		0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.721m		0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.721m		0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.721m		0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	3.870s		1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	3.870s		1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	3.870s		1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	26.590s		1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
		rom_ctrl_kmac_err_chk	7.980s		1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.265m		1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	18.150s		1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.721m		0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.839m		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.46721984138788630088182809345879347920542391843257508776088491613696997966614
      Line 108, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3662927ps failed at 3662927ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3673028ps failed at 3673028ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'