f0c640e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.910s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.570s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.710s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 30.620s | 1 | 1 | 100.00 | |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.240s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 22.440s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 4.540s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 13.040s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 59.250s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 3.000s | 1 | 1 | 100.00 | |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.780s | 1 | 1 | 100.00 | |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.070s | 1 | 1 | 100.00 | |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.710s | 0 | 1 | 0.00 | |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.040s | 1 | 1 | 100.00 | |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.380s | 1 | 1 | 100.00 | |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.860s | 1 | 1 | 100.00 | |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0.910s | 1 | 1 | 100.00 | |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 3.000s | 1 | 1 | 100.00 | |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.710s | 1 | 1 | 100.00 | |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.830s | 1 | 1 | 100.00 | |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.070s | 1 | 1 | 100.00 | |
| V1 | rom_read_access | rv_dm_rom_read_access | 1.250s | 1 | 1 | 100.00 | |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.610s | 1 | 1 | 100.00 | |
| V1 | csr_rw | rv_dm_csr_rw | 1.940s | 1 | 1 | 100.00 | |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 47.940s | 1 | 1 | 100.00 | |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 54.600s | 1 | 1 | 100.00 | |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0.730s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 54.600s | 1 | 1 | 100.00 | |
| rv_dm_csr_rw | 1.940s | 1 | 1 | 100.00 | |||
| V1 | mem_walk | rv_dm_mem_walk | 0.680s | 1 | 1 | 100.00 | |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.850s | 1 | 1 | 100.00 | |
| V1 | TOTAL | 25 | 27 | 92.59 | |||
| V2 | idcode | rv_dm_smoke | 2.910s | 1 | 1 | 100.00 | |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0.900s | 1 | 1 | 100.00 | |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.990s | 1 | 1 | 100.00 | |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.040s | 1 | 1 | 100.00 | |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.410s | 1 | 1 | 100.00 | |
| V2 | sba | rv_dm_sba_tl_access | 4.302m | 0 | 1 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 3.462m | 0 | 1 | 0.00 | |||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 2.198m | 0 | 1 | 0.00 | |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 5.724m | 0 | 1 | 0.00 | |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.790s | 0 | 1 | 0.00 | |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 2.330s | 1 | 1 | 100.00 | |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.110s | 1 | 1 | 100.00 | |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.990s | 0 | 1 | 0.00 | |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 6.680s | 1 | 1 | 100.00 | |
| rv_dm_tap_fsm_rand_reset | 0.770s | 0 | 1 | 0.00 | |||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.930s | 1 | 1 | 100.00 | |
| V2 | stress_all | rv_dm_stress_all | 0 | 1 | 0.00 | ||
| V2 | alert_test | rv_dm_alert_test | 0.680s | 1 | 1 | 100.00 | |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 2.190s | 1 | 1 | 100.00 | |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 2.190s | 1 | 1 | 100.00 | |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 54.600s | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.610s | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.940s | 1 | 1 | 100.00 | |||
| rv_dm_same_csr_outstanding | 5.830s | 1 | 1 | 100.00 | |||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 54.600s | 1 | 1 | 100.00 | |
| rv_dm_csr_hw_reset | 1.610s | 1 | 1 | 100.00 | |||
| rv_dm_csr_rw | 1.940s | 1 | 1 | 100.00 | |||
| rv_dm_same_csr_outstanding | 5.830s | 1 | 1 | 100.00 | |||
| V2 | TOTAL | 11 | 19 | 57.89 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 3.340s | 1 | 1 | 100.00 | |
| rv_dm_tl_intg_err | 6.440s | 1 | 1 | 100.00 | |||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 6.440s | 1 | 1 | 100.00 | |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.330s | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.840s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.330s | 1 | 1 | 100.00 | |
| rv_dm_debug_disabled | 0.840s | 0 | 1 | 0.00 | |||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 2.910s | 1 | 1 | 100.00 | |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.180s | 1 | 1 | 100.00 | |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.900s | 1 | 1 | 100.00 | |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 0.900s | 1 | 1 | 100.00 | |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.180s | 1 | 1 | 100.00 | |
| V2S | TOTAL | 4 | 5 | 80.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.890s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 9.633m | 0 | 1 | 0.00 | ||
| TOTAL | 40 | 53 | 75.47 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.110321158951746199803557467843071139381791142426657925112458526727025226876049
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.21589717331145504938730660708301610789244250329853844691981775337575180343778
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.26683080572265638836828904364794038634066267611356340821591323308721893621755
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.106416454454807910870128415487660725151808309418441903969322885588361175195891
Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.54906088181283465327892819015382852938773266430933316866272215658153004341755
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7266) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.44488165890773160315335645617195531741562992553603052683005586751288478970893
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 31756573 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7266) { a_addr: 'h20576670 a_data: 'h39dfe442 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h19efe d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 31756573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:
0.rv_dm_mem_tl_access_resuming.27340924023053740914679208616398672161370193122956010314551260463306347481629
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 121838086 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 121838086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:
0.rv_dm_hart_unavail.56583436911253330490854466663248581165943433036876369671798400794231241237692
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 80059891 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 80059891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
0.rv_dm_jtag_dmi_debug_disabled.111092696281070937911598570155751198529279471972891105538668082405220009736257
Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 264346580 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (998502090 [0x3b83eeca] vs 0 [0x0])
UVM_INFO @ 264346580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(($rose(mem_tl_d_o_i.d_valid) && (!debug_enabled)) -> mem_tl_d_o_i.d_error)' has 1 failures:
0.rv_dm_debug_disabled.4394408928227031789394740147010648308888076062956143549732355254345941620170
Line 78, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest/run.log
Offending '(($rose(mem_tl_d_o_i.d_valid) && (!debug_enabled)) -> mem_tl_d_o_i.d_error)'
UVM_ERROR @ 55200268 ps: (rv_dm_enable_checker.sv:46) [ASSERT FAILED] MemTLResponseWithoutDebugIsError_A
UVM_INFO @ 55200268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
0.rv_dm_stress_all.38263138792158016871176523047902990337587663395440829657401440212205772857156
Log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
Job timed out after 180 minutes
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7536) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.66484676795860168626330677268031111557439467194492617609226449414772288104682
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 91306087 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7536) { a_addr: 'h45225568 a_data: 'he9441af a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4a a_opcode: 'h4 a_user: 'h193c5 d_param: 'h0 d_source: 'h4a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 91306087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6166) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.102204370880950922656879591789947384216206984435811713130953647426600737842238
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 65649984 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6166) { a_addr: 'h2f15c5f0 a_data: 'h19f46b22 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h67 a_opcode: 'h4 a_user: 'h18969 d_param: 'h0 d_source: 'h67 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 65649984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---