SPI_HOST Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	15.000s	1.279ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	45.829us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	18.495us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	527.043us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	99.860us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	195.693us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	18.495us	1	1	100.00
		spi_host_csr_aliasing	1.000s	99.860us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	23.763us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	16.645us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	68.721us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	73.224us	1	1	100.00
		spi_host_error_cmd	2.000s	15.287us	1	1	100.00
		spi_host_event	15.000s	2.889ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	66.731us	1	1	100.00
V2	speed	spi_host_speed	2.000s	66.731us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	66.731us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	124.283us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	27.209us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	66.731us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	66.731us	1	1	100.00
V2	duplex	spi_host_smoke	15.000s	1.279ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	15.000s	1.279ms	1	1	100.00
V2	stress_all	spi_host_stress_all	7.000s	382.828us	1	1	100.00
V2	spien	spi_host_spien	10.000s	566.983us	1	1	100.00
V2	stall	spi_host_status_stall	36.000s	2.789ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	1.000s	42.730us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	73.224us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	23.255us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	24.563us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	490.956us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	490.956us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	45.829us	1	1	100.00
		spi_host_csr_rw	1.000s	18.495us	1	1	100.00
		spi_host_csr_aliasing	1.000s	99.860us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	34.184us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	45.829us	1	1	100.00
		spi_host_csr_rw	1.000s	18.495us	1	1	100.00
		spi_host_csr_aliasing	1.000s	99.860us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	34.184us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	181.168us	1	1	100.00
		spi_host_sec_cm	2.000s	278.713us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	181.168us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.617m	26.668ms	1	1	100.00
		TOTAL			26	26	100.00