SRAM_CTRL/RET Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.640s		1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s		1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.810s		1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.690s		1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.850s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.000s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.810s		1	1	100.00
		sram_ctrl_csr_aliasing	0.850s		1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.120s		1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.440s		1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.008m		1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.442m		1	1	100.00
V2	bijection	sram_ctrl_bijection	23.440s		1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.283m		1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.190s		1	1	100.00
V2	executable	sram_ctrl_executable	12.237m		1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.230s		1	1	100.00
		sram_ctrl_partial_access_b2b	5.175m		1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.570s		1	1	100.00
		sram_ctrl_throughput_w_partial_write	39.530s		1	1	100.00
		sram_ctrl_throughput_w_readback	30.570s		1	1	100.00
V2	regwen	sram_ctrl_regwen	1.773m		1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.690s		1	1	100.00
V2	stress_all	sram_ctrl_stress_all	33.202m		1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.620s		1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.100s		1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.100s		1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s		1	1	100.00
		sram_ctrl_csr_rw	0.810s		1	1	100.00
		sram_ctrl_csr_aliasing	0.850s		1	1	100.00
		sram_ctrl_same_csr_outstanding	1.040s		1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s		1	1	100.00
		sram_ctrl_csr_rw	0.810s		1	1	100.00
		sram_ctrl_csr_aliasing	0.850s		1	1	100.00
		sram_ctrl_same_csr_outstanding	1.040s		1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.660s		1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.670s		0	1	0.00
		sram_ctrl_tl_intg_err	2.740s		1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.670s		0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.740s		1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.773m		1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.773m		1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.810s		1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.237m		1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.237m		1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.237m		1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.190s		1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.810s		1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.660s		1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.910s		0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.640s		1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.640s		1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.237m		1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.670s		0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.190s		1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.670s		0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.670s		0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.640s		1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.670s		0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.241m		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.74064444714794808042452103641849606844754175453845284420728823205083941865534
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 137544386 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x3d)
        UVM_INFO @ 137544386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.25620998676121191007516005054528703154464085522517831922031319666734691974285
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  16818769 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  16818769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---