UART Simulation Results

Thursday November 06 2025 16:04:48 UTC

GitHub Revision: f0c640e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.540s		1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.830s		1	1	100.00
V1	csr_rw	uart_csr_rw	0.700s		1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.770s		1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.760s		1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.790s		1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.700s		1	1	100.00
		uart_csr_aliasing	0.760s		1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	17.050s		1	1	100.00
V2	parity	uart_smoke	1.540s		1	1	100.00
		uart_tx_rx	17.050s		1	1	100.00
V2	parity_error	uart_intr	9.790s		1	1	100.00
		uart_rx_parity_err	36.680s		1	1	100.00
V2	watermark	uart_tx_rx	17.050s		1	1	100.00
		uart_intr	9.790s		1	1	100.00
V2	fifo_full	uart_fifo_full	8.100s		1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	25.170s		1	1	100.00
V2	fifo_reset	uart_fifo_reset	32.880s		1	1	100.00
V2	rx_frame_err	uart_intr	9.790s		1	1	100.00
V2	rx_break_err	uart_intr	9.790s		1	1	100.00
V2	rx_timeout	uart_intr	9.790s		1	1	100.00
V2	perf	uart_perf	12.976m		1	1	100.00
V2	sys_loopback	uart_loopback	4.000s		1	1	100.00
V2	line_loopback	uart_loopback	4.000s		1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.250s		0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.630s		1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.910s		1	1	100.00
V2	rx_oversample	uart_rx_oversample	26.280s		1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.747m		1	1	100.00
V2	stress_all	uart_stress_all	28.320s		1	1	100.00
V2	alert_test	uart_alert_test	0.660s		1	1	100.00
V2	intr_test	uart_intr_test	0.660s		1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.330s		1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.330s		1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.830s		1	1	100.00
		uart_csr_rw	0.700s		1	1	100.00
		uart_csr_aliasing	0.760s		1	1	100.00
		uart_same_csr_outstanding	0.970s		1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.830s		1	1	100.00
		uart_csr_rw	0.700s		1	1	100.00
		uart_csr_aliasing	0.760s		1	1	100.00
		uart_same_csr_outstanding	0.970s		1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.170s		1	1	100.00
		uart_tl_intg_err	1.330s		1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s		1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	47.780s		1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.54652943371293997329623093074387097812863133771045936853439085764567266531670
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  93510132 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @  93520132 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @  93530132 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 231 [0xe7]) reg name: uart_reg_block.rdata
        UVM_ERROR @  93540132 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @  93550132 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata